User Manual

2-8 EP7309/11/12 User’s Manual - DS508UM4
Copyright Cirrus Logic, Inc. 2003
CPU Core
2
User mode in Th u mb state generally limits access to r0-r7. There are a few
instructions that allow access to the high r egisters. For the 5 exceptions, the processor
must revert to ARM state.
R0-R12: Ge neral purp o se read/write 32-bi t registers
R13 (sp): Stack Pointer
R14 (lr): Link Register
R15 (pc): Program Counter
CPSR: Current Program Status Register (contains condition codes and
operating modes)
SPSR: Saved Program Status Register ( saves CPSR when exception occurs)
ARM720T Core Coprocessor Registers
The ARM720T core ha s 16 coprocessor registers for control over the MMU . See Table
2-2 on page 2-9 U pdates to the co- processor registers are written using the CP15
instruction.
Figure 2-3. Register Organization Summary
r0
r6
r5
r4
r3
r2
r1
cpsr
r15 (p c)
r14 (lr)
r13 (sp)
r12
r11
r10
r9
r14 (lr)
r13 (sp)
r12
r11
r10
r9
sp sr
Banked
Banked
r8
r7
r8
User FIQ IRQ SVC Undef Abort
Thum b state
Low registers
r14 (lr)
r13 (sp)
sp sr
Banked
r14 (lr)
r13 (sp )
spsr
Banked
r14 (lr)
r13 (sp )
spsr
Banked
r14 (lr)
r13 (sp)
sp sr
Thum b state
High registers