User Manual

EP7309/11/12 Users Manual - DS508UM4 2-7
Copyright Cirrus Logic, Inc. 2003
CPU Core
22
2
Debug Interface
JTAG (Joint Test Action Group) or IEEE 1149 provides a boun dary scan test interface
with 5 dedicated signals c onnected directory to the CPU core:
•TRST-TestReset(activelow)
•TCK-TestClock
TMS - Test Mode Select
•TDI-TestDataIn
•TDO-TestDataOut
See Chapter 14 for more information on debugging the EP73xx via the JTAG interface.
CPU Register Definitions
ARM has 37 32-bit internal registers. If operating in Thumb mode, the processor m ust
switch to ARM mode before taking an exception. The return instruction will restore
the processor to Thu mb state. Most tasks are executed out of U ser mode.
User: Unprivileged normal operating mode.
FIQ: Fast interrupt (high priority) mode when FIQ is asserted
IRQ: Interrupt request (normal) mode when IRQ is asserted
Supervisor: Software interrupt instruction (SWI) or reset will cause entry into
this mode
Abort: Memory ac cess violation will cause entry into this mode
Undef: Undefined instructions
System: Privileged mode. Uses sam e registers as user mode
Figure 2-3 on page 2-8 illustrates the use of all registers for the following core
operating modes. E ach will b ank or store a specific number of registers. Banked
register information is not shared between modes. FIQs bank the fewest number of
registers which i nc reases p erformance.