User Manual

2-6 EP7309/11/12 User’s Manual - DS508UM4
Copyright Cirrus Logic, Inc. 2003
CPU Core
2
Cache i s direct-mapped. The copy of the address or data is stored along with an
address tag that is compared with the location in system memory. Cache is also write-
through and uses a replacement algorithm to s elect which of the four possible
locations will be overwritten in the case of a cache miss.
Write Buffer
The write buffer holds four addresses a nd eight data words.The MMU defines which
addresses are bufferable. Each address can be associated with an y number of data
words. Data words are written to sequential memory s tarting at that address.
The write buffer becomes full when all f our addresses are u sed or all eight data words
are used. The p rocessor can w rite into the write bu ffer at fast cache speed and
continue executing instructions stored in cache while the write buffer stores data to
external memory at the cur rent memory bus speed. If there is a memory fault
generated by a buffered write, the system will not be able to recover from it since the
processor state is not recoverable.
Figure 2-2. ARM720T Cache Organization
encode
Data RAM
2048 x 32-bit
word
tag R A M
128 entry
ta g R AM
128 entry
ta g R AM
128 entry
ta g R AM
128 entry
=? =? =? =?
31 11 10 43210
[1:0 ]
[8:2 ]
[10:9]
[10:0]
hit data
byte
addresses
virtual ad dress