User Manual

EP7309/11/12 User’s Manual - DS508UM4 2-5
Copyright Cirrus Logic, Inc. 2003
CPU Core
22
2
TLB
The TLB ( Tr anslation look-aside Buffer) is a 64-entry associative cache of recent
virtual address to physical address translations to eliminate a two-stage search for a
higher p roportion of internal register or external bus accesses.
• Provides the translation and access permission information for memory
accesses
• For a TLB miss, the TLB w alking hardware accesses the transition table
from physical memory to update itself (two-stage).
• If the TLB is full, a s tored v alue will be over-written.
Cache
Cache is 4-way set associative with 8 Kbytes of mixed instruction and data, organized
as 512 lines of 4 words (16-byte). Connected directly to the core, cache only stores the
virtual address. Cache can on ly be u sed once the MMU is enabled. On ce enabled, the
specific sections or pages of memory that are segmented can control whether cache or
write buffer is used for that region. C ache is disabled at pow er on reset. See Figure
2-2 on page 2-6 for cache organization.