User Manual

2-4 EP7309/11/12 User’s Manual - DS508UM4

CPU Core

Operational Overview

Using the Von Neumann ( load/store) architecture, the ARM720T core has a three

stage instruction pipeline to increase the speed of th e instruction execution within th e

processor. The fetch-decode-exec ute of concurrent instructions are done in parallel

requiring approximately 1.9 CPI (cycles per instruction).

The core provides a 8 Kbytes unified cache and a m emory management unit ( MMU ).

The MMU supports a two-level page table arran gement and controls the cache and

write buffer for each page created.

ARM720T core h as 37 32-bit registers: 1-program counter, 1-current p rogram s tatus

supports 16 co-processor registers for control of the on-chip cac he, MMU, an d buffers.

Thecoresupportstwoinstructionsets,ARMandThumbforfull32-bitor16-bit

instruction decoding. State switching between ARM and Thumb, and register

assignments for each, are detailed in the ARM720T document provided by ARM. The

core supports both big a s wel l as little-endian modes.

The core contains an embedded debug architecture. The 5-pin JTAG port will allow

the host s ystem to convert debugger com man ds into JTAG comm ands for the

purpose of h ardware control to do the fol lowing:

• Set breakpoints and watchpoints

•HalttheARMprocessor

• Access internal registers

• Access system memory

MMU

The MMU (Memory Management Unit) does the following

• Translates virtual addresses to physical addresses

• Controls memory access permissions, cache and write buffer accesses for

each p age.

The MMU consists of a TLB (translation look aside buffer) and h ardware for p age

table accesses as w ell as the access control logic.

Memory is divided by the MMU in the following manner:

• Sections: 1 Mbyte memory blocks

• Large Page: 64 Kbytes memory blocks w hich allows mapping of large

region with only a single entry in the TLB.

• Small Page: 4 Kbytes memory blocks

Based on the entry for the section or page, the cache and write buffer will be either

enabled or disabled for that region of memory.