User Manual

EP7309/11/12 User’s Manual - DS508UM4 2-1

Chapter 2

2CPU Core

Introduction

The 7312 processor utilizes th e ARM720T which is based on the ARM7TDMI RISC

(Reduced Instruction Set Computer) core running at a dynamically programmable

speed from 18-90 MHz. This chapter discusses the key features of the ARM core.

Features

Key features include:

• ARM7TD MI C PU core (which supports th e log ic for the Thumb instruction

set, core debug, enhanced multiplier, JTAG, and the Embedded ICE)

running at a dynamically programmable clock speeds.

• Memory Management Unit (MMU) compatible with the ARM710 core

(providing address tran slation and a 64-entry translation lookaside buffer)

with added support for Windows CE.

• 8 Kbytes of unified instruction and data c ache with a four-way set

associative cache controller.

• Write Buffer

• TLB (Translation Look-Aside Buffer)

• System State Control: Operating, Idle, Standby

•CPUClockOptions

• System R eset Options

• CPU and Co-processor Registers

Programming Register List

Table 2-1: Programming Registers

Address Name Type Size Description Page

0x8000.0840 STDBY Write Write Enters Standby State page 2-13

0x8000.0800 HALT Write Write enters Idle State page 2-13

0x8000.2610 PLL Write 8 Write register for PLL Multiplier page 2-11

0x8000.A5A8 PLL Read 8 Read Register for PLL Multiplier page 2-11