User Manual

17-4 EP7309/11/12 User’s Manual - DS508UM4
Copyright Cirrus Logic, Inc. 2003
UART and SIR Encoder
17
enabled) is half-empty. Same condition applies during transmit if the FIFOs are not
enabled. An interrupt will be generated when there is no data in the UART h olding
register. The third interrupt is the modem interrupt UMSINT and will be active if
either th e two modem status l ines (CTS or D T S) change state
SIR Encoder
UART1 shares its FIFOs with an IrDA (Infrared Data Association) SIR protocol
encoder. This encoder can be enabled from SYSCON1 at SIREN (bit 15). U A RT1 must
be en abled for the encoder to work. Data is sent a n d received by the en coder using
theUARTdataholdingregister.TheSIRandUART1sharethesamedataholding
register and FIF0s. On ce the SI R encoder is enabled, is controls UART1.
The SIR encoder output pin is
LEDDRV and input is received from PHDIN.Themodem
lines can still cause an interrupt irrespective of the SIR activity and can be masked if
necessary.
SYSCON1 bit 20 c ontrols the encoding strategy for transmitting zeros in the bit
stream. A zero in this field can be represented by a p ulse width of 3/16th of the bit
rate period or a pulse width of 3/16th of a 115. 2k bit rate clock (regardless of selected
bit rate). Actual bit rate is selected by the UART1 bit rate clock.
UART2
UART2 sup ports on ly two interrupts, Rx and Tx in the same ma n ner as UART1. It
does not possess the additional control lines CTS, DTS. UART2 is enabled in
SYSCON2 register bit 8.