User Manual

EP7309/11/12 User’s Manual - DS508UM4 17-3
Copyright Cirrus Logic, Inc. 2003
UART and SIR Encoder
1717
17
UART1
UART 1 supports three modem control signals CTS, DTS, an d DCD . The additional R I
input, RTS and DTS output modem control lines are not explicitly supported but can
be i mplemented by using GPIO pins. UART1 is enabled in SYSCON1 at UART1EN
(bit 8).
Programming the UART configuration is done via the UBRLCR1-2 register.The input
and output register where data is sent an d received from the FIFOs can be accessed
viatheUART1-2data(holding)register.
Three interrupts can be generated by UART1: Rx, Tx, and modem status interrupts.
The Rx interrupt is generated when the FIFO (if enabled) is half-full, or is non-empty
for longer than three character length times wi th no more characters being received. If
the FIFOs are n ot enabled, the interrupt can occur when there is data in the UART1
holding register. The transmit interrupt can occur if the internal transmit FIFO (if
Table 17-3: UART Bit Rate in PLL Clock Mode (74 MHz)
Divisor Value
Bit Rate Running from
the PLL Clock
0 —
1 115200
2 76800
3 57600
5 38400
11 19200
15 14400
23 9600
95 2400
191 1200
2094 110
Table 17-4: UART Bit Rate from 13 MHz Clock
Divisor Value
Bit Rate Running from
13 MHz Clock
Error on
13 MHz Value
0 116071 0.75%
1 58036 0.75%
2 36890 0.75%
5 19345 0.75%
7 9673 0.75%
47 2416 0.42%
96 1196 0.28%
1054 110.02 0.18%