User Manual

EP7309/11/12 User’s Manual - DS508UM4 16-19
Copyright Cirrus Logic, Inc. 2003
DAI/CODEC/SSI2
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down to th e bottom, the Right Channel Transmit logic uses the new value within th e
FIFO for tran sm ission. When the RCTU bit i s set, an interrupt request is made.
RCRO:
The Right C hannel Receive FIFO Overrun Status Bit ( RCRO) is set when the right
channel receive logic attemp ts to place data into the Right C hannel Receive FIFO after
it has been completely filled. Each time a new piece of data is received, the set signal
to the R CR O status bit is asserted, and the newly received data i s discarded. This
process is repeated for each new sample received until at least one empty FIFO entr y
exists. W h en the RCRO bit is set, an interrupt requ est is made.
LCTU:
The Left Channel Transmit FIFO Underrun Status Bit (LCTU) is set when the Left
Channel Transmit logic attempts to fetch data from the F IFO after it has been
completely emptied. When an underrun occurs, the Left Channel Transmit logic
continuously transmits the last valid left channel value which was transmitted before
the underrun oc cu rred. O nce data is placed in the F IFO and it i s transferred down to
the bottom, th e Left Channel Transmit logic uses th e new value within th e FIFO for
transmission. W h en the LCTU bit is set, an i nterrupt request is made.
LCRO:
The Left Channel Receive FIFO Overrun Status Bit (LCRO) is set when th e Left
Channel R eceive logic p laces data into the Left Channel Receive FIFO after it h as been
completely filled. Each time a new piece of data is received, the set signal to the LCRO
status b it is asserted, and the newly received sam ple is discarded. Th is process is
repeated for each new piece of data received u ntil at least on e empty FIFO entry
exists. When the LCRO bit is set, an i nterrupt request is made.
RCNF:
The Right Channel Transmit FIFO Not Full Flag (RCNF) is a read-only bit which is set
whenever th e Right Channel Transmit FIFO contains one or more entries which do
not contain valid data and is cleared when the FIFO is completely full. This bit can be
polled when using programmed I/O to fill the Right Channel Transmit FIFO. This bit
does not request an inter rupt.
LCNF:
The Left Channel Transmit FIFO Not Full Flag (LCNF) is a read-only bit which is set
when ever the Left Channel Transm it FIFO contains one or more entries which do not
contain valid data. It is cleared when the FIFO is completely full. This bit can be
polled when using programmed I/O to fill the Left Channel Transmit FIFO. This bit
does not request an inter rupt.
LCNE:
The Left Channel Receive FIFO Not Empty Flag (LCNE) is a read-only bit which is set
when ever the Left Channel Receive FIFO contains one or more entries of valid data
and is cleared when it no longer contains any val id data. Th is bit can be polled when
using programmed I/O to remove remaining data from the receive FIFO. This bit
does not request an inter rupt.