User Manual

16-16 EP7309/11/12 User’s Manual - DS508UM4
Copyright Cirrus Logic, Inc. 2003
DAI/CODEC/SSI2
16
DAI Data Register 2 (DAIDR2)
Address: 0x8000.2080, Read / Write
Bit Descriptions:
FIFOEN: FIFO Transmit Bit
0 - Disable Transmit, 1 - Enable Transmit
FIFO Channel Select:FIFO Channel Select
01101b - Left channel select, 10001b - Right channel select
DAIDR2 is a 32-bit register that utilizes 21 bits and is used to enable and disable the
FIFOs for the left and right channels of the DAI data stream. The lef t channel FIFO is
enabled b y writing 0x000D.8000 and disabled b y writing 0x000D.0000. The right
channel FIFO i s enabled by writing 0x0011.8000 an d disabled by writing 0x0011.0000.
After writing a value to th is register, wait u ntil the FIFO operation complete bit
(FIFO) is set in th e DAI status register before writing another value to this register.
DAI Status Register (DAISR)
Address: 0x8000.2100, Read / Write
Bit Descriptions:
(See f ull bit des cription for com plete details)
RCTS: Right Channel Transmit FIFO Service Request F lag (read only)
0 - Right Channel Transmit FIFO is more than half full (five entries
or more are filled) or DAI is disabled.
1- Right Channel Transmit FIFO is more than half full or less (four
or fewer entries filled) and the DAI operation is enabled.
RTCM = 1.
RCRS: Right Channel R eceive F IFO Service Request Flag (read only)
0-RightChannelReceiveFIFOismorethanhalffull(fiveentries
or f ewer are filled) or DAI is disabled.
1-RightChannelReceiveFIFOismorethanhalffullorless(sixor
more entries filled) and the D AI operation is en abled. RTCM = 1.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD FIFO Channel Select
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOEN RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD FIFO LCNE LCNF RCNE RCNF LCRO LCTU RCRO RCTU LCRS LCTS RCRS RCTS