User Manual

16-14 EP7309/11/12 User’s Manual - DS508UM4
Copyright Cirrus Logic, Inc. 2003
DAI/CODEC/SSI2
16
RCTM:
The Left Channel Sample Receive FIFO interrupt mask (LCRM) bit is u sed to mask or
enable the Left Channel Receive FIFO service request interru pt. When LCRM = 0, the
interrupt is masked and the state of the left channel sample receive FIFO s ervice
request (LCRS) bit within the DAI status register is ignored by th e interrupt
controller. W h en LCRM = 1, the interrupt is enab led and whenever LCR S is set ( one)
an interrupt request is ma de to the interrupt controller. Note that p rogramming
LCRM = 0 does not affect the current state of LCRS or the Left C hannel Receive FIFO
logic’s ability to set and clear LCRS, it only blocks the generation of the interrupt
request.
RCRM:
The Right C hannel Receive FIFO interrupt mask (RCRM) bit i s used to mask or
enable th e Right Channel Receive FIFO service request interrupt. When RCRM = 0,
the interrupt is m asked and the state of the Right Channel Receive FIFO service
request (RCRS) bit within the DAI status register is ignored by the interrupt
controller. When RCRM = 1, the interrupt is enabled, and whenever RCRS is set (one),
an interrupt request is ma de to the interrupt controller. Note that p rogramming
RCRM = 0 does not affect the current state of RCRS or the Right Channel Receive
FIFO logic’s ability to set and clear RCRS, for it only blocks the generation of the
interrupt request.
DAI Data Register 0 (DAIDR0)
Address: 0x8000.2040, Read / Write
Bit Descriptions:
[0:15]: Bottom Right Receive and Top Right Transmit FIFO. Data is filed
and extracted from the Right C hannel FIFOs using this register.
Data Read: Data received by the DAI m achine from external hardware and is
placed th e top of the receive FIFO and shifted down for each n ew
entry into the FIFO until it reaches the last empty location within
the FIFO. Data is removed from the FIFO by a system software
read from the bottom of th e FIFO. The bottom value is the
replaced by the n ext value as all information with th e FIFO is then
shifted down one location.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bottom Right Channel Receive FIFO / Top Right Channel Transmit FIFO