User Manual

EP7309/11/12 User’s Manual - DS508UM4 16-13
Copyright Cirrus Logic, Inc. 2003
DAI/CODEC/SSI2
1616
16
Full Bit Descriptions
DAIEN:
When the DAI is disabled, all of its clocks are powered down to minimize power
consumption. Note that DAIEN is the only control bit within the DAI interface that is
reset to a know n state. It is cleared to zero to ensure th e DAI timing is disabled
following a reset of the device.
When the DAI tim ing is enab led,
SCLK b egins to transition and the start of the first
frame is signaled by driving the
LRCK pin low. The rising and falling-edge of LRCK
coincides with the rising and falling-edge of SCLK.AslongastheDAIENbitisset,
the DAI interface operates continuou sly, transmitting and receiving 128 bit data
frames. When the DAIEN bit is cleared, the DAI interface is disabled immediately,
causing the current fram e which is being transmitted to be terminated. Clearing
DAIEN resets the DAI’s interface FIFOs. However DAI data register 2, th e control
register, and the status register a re n ot reset. Therefore, the user must ensure these
registers are properly reconfigured before re-enabling the DAI interface.
LCTM/LRCM/RCTM/RRCM:
The DAI interface can generate four m askable interrupts and four non-maskable
interrupts, as described in the sections below. Only one i nterrupt line is wired into the
interrup t controller for the whole DAI interfac e. This interrupt is the wired OR of al l
eight interrupts (after masking where ap propriate). The software servicing the
interrup ts must read the status register in th e DAI to d etermine which source(s)
caused the interrupt. It is possible to prevent any DAI sources causing an interrupt by
masking the DAI interrupt in the interrup t controller register.
LCTM:
TheLeftChannelSampleTransmitFIFOinterruptmask(LCTM)bitisusedtomask
or enable the left channel sample transmit FIFO service request interrupt. When
LCTM = 0, the interrupt is masked and the state of the left channel Transmit FIFO
service request (LCTS) bit within the DAI status register i s ignored by the interrupt
controller. When LCTM = 1, the inter rupt is enabled an d whenever LCTS is set (one)
an interrupt request is made to th e interrupt controller. Note that programming
LCTM=0doesnotaffectthecurrentstateofLCTSortheLeftChannelTransmitFIFO
logic’s ability to set and clear LCTS; it only blocks the generation of the interrupt
request.
LCRM:
TheLeftChannelSampleTransmitFIFOinterruptmask(LCTM)bitisusedtomask
or enable the left channel sample transmit FIFO service request interrupt. When
LATM = 0, the interrupt is masked a nd the state of the Left Chan nel Transmit FIFO
service request (LCTS) bit within the DAI status register i s ignored by the interrupt
controller. When LCTM = 1, the inter rupt is enabled an d whenever LCTS is set (one)
an interrupt request is made to th e interrupt controller. Note that programming
LCTM=0doesnotaffectthecurrentstateofLCTSortheLeftChannelTransmitFIFO
logic’s ability to set and clear LCTS; it only blocks the generation of the interrupt
request.