User Manual

EP7309/11/12 User’s Manual - DS508UM4 16-11
Copyright Cirrus Logic, Inc. 2003
DAI/CODEC/SSI2
1616
16
causes the sync and interrupt gene ra tion logic to become active; otherwise they are
disab led to conserve power.
Data is loaded into the transmit FIFO by writing to th e CODR register. At the
beginning of a transmit cycle, this data is loaded into a shift/load register. Just prior
to the by te being transferred ou t,
PCMSYNC goes high for one PCMCLK cycle. T hen
the data is shifted out serially to
PCMOUT, MSB first, (with the MSB valid at the sam e
time
PCMSYNC is asserted). Data is shifted on the rising edge of the PCMCLK output.
Receiving of data is performed by taking data in serially thr ough
PCMIN,againMSB
first, shifting it through the shift/load register and loading the com pl ete byte into the
receive FIFO. If th ere is n o data available in th e transmit FIFO, then a zero will b e
loaded i nto the shift/load register. Input data is sampled on the falling edge of
PCMCLK.DataisreadfromtheCODRregister.
DAI/CODEC/SSI2 Register Descriptions
DAI Registers
DAI Mode Control Register (DAI64FS)
Address: 0x8000.2600, Read / Write
Bit Descriptions:
I2SF64: 0=128 Fs mode. SYSCON3 bit 9 must be set for128 F s mode.
1=64 Fs mode. SY SCON3 bit 9 must be c leared 64 Fs mode
AUDCLKEN:1 = Enable the audio clock generator for the DAI machine.
AUDCLKSRC:Audio clock source. 0=73.728 or 90.3168 MHz (PLL).
1=11.2896 MHz (external
MCLK)
MCLK256EN:1=Enables
MCLK(BUZ) (256 Fs) 0=Enables BUZ pin for
annunciator. See SYSCON chapter for details.
LOOPBACK:Test mode. Loops digital data internally. Data normally going to
the DAC loops back internally.
AUDIV: Frequency divisor for the sample frequency and bit clock using
either th e external clock or the PLL cl ock for the audio clock
generator. (See table above)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD AUDIV RSVD Loopba
ck
RSVD MLCKE
N
AUDCL
KSRC
AUDIOC
LKEN
I2SF64