User Manual

EP7309/11/12 User’s Manual - DS508UM4 16-7

DAI/CODEC/SSI2

1616

Data is read an d written from the DAI data register for both the left an d right

channels. T he internal FIFOs for both channel shift the data accordingly to proper

reads from the system, an d w rites to th e system.

Master/Slave SSI2 Interface

A second SPI/Microwire interface w ith full master/slave capability is provided by

the EP73XX. Data rates in slave mode are theoretically up to 512 kbits/s, full duplex,

although continuous operation at this data rate will give an interrupt rate of 2 kHz,

which is too fast for many operating systems. This would require a worst-case

interruptresponsetimeoflessthan0.5msandwouldcauselossofdatathroughTX

underruns a nd RX ove rruns.

The interface is fully capable of being clocked at 512 kHz when in slave mode.

However, it is anticipated that external h ardware will be used to frame th e data into

packets. Th erefore, althou gh the data wou ld be transmitted at a rate of 512 kbits/s,

the sustained data rate would in fact only be 85.3 k bits/s (i.e., 1 by te every 750 µsec).

At this data rate, the required interrupt rate will be greater than 1 ms, which is

acceptable.

There are separate half-word-wide RX and TX FIFOs (16 half-words each) and

corresponding interrupts which are generated when the FIFO’s are half-full or half-

empty as appropriate. The interrupts are called SS2RX and SS2TX, respectively.

There are five pins to support this SSI port:

SSIRXDA, SSITXFR, SSICLK, SSITXDA,and

SSIRXFR.TheSSICLK, SSIRXDA, SSIRXFR,andSSITXFR signals a re inputs and the

SSITXDA signal is an output in s lave mode. I n the master mode, SSICLK, SSITXDA,

SSITXFR,andSSIRXFR are outputs, and SSIRXDA is an input. Master mode is enabled

by writing a one to th e SS2MAEN bit (SYSCON2[9]). W hen the master/slave SSI is

not required, it can be disabled to save power by writing a zero to the SS2TXEN and

the SS2RXEN bits (SYSCON 2[4] [7]). When set, these two bits independently enabl e

thetransmitandreceivesidesoftheinterface.

The master/slave SSI is synchronous, full duplex, and capable of supporting serial

data transfers between two nodes. Although the i nterface is byte-oriented, data is

loaded in blocks of two bytes at a time. Each data byte to be tran sferred is marked by

a frame sync pulse, lasting one clock period, and located one clock prior to the first bit

being transferred. D irection of the SSI 2 ports, in s lave and master m ode, is shown in

Figure 16-3.