User Manual

EP7309/11/12 User’s Manual - DS508UM4 16-5
Copyright Cirrus Logic, Inc. 2003
DAI/CODEC/SSI2
1616
16
DAI Clock Generation
The DAI contains a series of programmable clocks to s upp ort a wi de variety of
sample rates. A graphical representation of the DAI clock s cheme is contained in
Figure 16-2.
Two sources for the clock network are available. The first is the internal 73.728 MHz
PLL clock. Using th is clock, sample rates of 8 kHz, 16 kHz, 24 kHz, 32 k Hz, and
48 kH z are available. The other clock comes f rom an external source which must
output an 11.286 MHz signal. The programmable audio divider will then divide this
signal to provide
SCLK, LRCLK and MCLK(BUZ) for the desired sample rates.
When running at 90 MHz, the 11.025, 22.050, and 44.1 kHz sample frequencies c an be
obtained directly without the use of an 11.2896 MHz external clock. However, to
directly obtain 12, 24, and 48 kHz sample frequencies at 90 MHz a 12.288 MHz
external clock is needed. However, samp le frequencies not attainable directly c an be
obtained by sample rate conversion.
Table 16-5 details the programmable divider values for all of the individual sample
rates and their corresponding frequencies for
SCLK.
* Optional 11.2896 MHz external clock
Table 16-5: Programmable Audio Divisors at 74 MHz
Clock
Source (MHz)
Sample
Frequency (kHz)
128 Fs
Audio Bit Clock
(MHz)
64 Fs
Audio Bit Clock
(MHz)
128/64 Fs
Divisor
(AUDIV)
73.728 8 1.0240 0.5120 36
*11.2896 11.025 1.4112 0.7056 8
73.728 12 1.5360 0.7680 24
73.728 16 2.048 1.024 18
*11.2896 22.050 2.8224 1.4112 4
73.728 24 3.0720 1.5360 12
73.728 32 4.0960 2.0480 9
*11.2896 44.1 5.6448 2.8224 2
73.728 48 6.1440 3.0720 6
PLL
(90.3168 MHz)
EXTCLK
(11.2896 MHz)
(12.288 MHz)
/2
MUX
(AUDCLKSRC)
Programmable Divide
(AUDIV)
128/64(Fs)
/32
Audio Bit Clock 128/64(Fs)
SCLK
/128
/64
LRCLK(Fs)
MCLK (BUZ)
7-bit
counter
fixed at 4
Audio
Sample
Frequency
(Fs)
Audio Data
FIFO
Control
Figure 16-2. Digital Audio Clock Generation