User Manual

EP7309/11/12 User’s Manual - DS508UM4 15-3
Copyright Cirrus Logic, Inc. 2003
SSI Port
1515
15
interfaced to DSP style converters such as the Analog Devices’ AD7811/12 using
nADCCS as a common RFS/TFS line.
Unlike the SSI2/DAI/CODE C interface, SSI1 has a dedicated set of I/O p ins and does
not require an elaborate initialization p rocedure.
The clock output frequency is prog rammab le and only active during data
transmissions to save power. There are four output frequencies selectable, wh ich will
be s lightly different d epending whether the device is operating in a 13 M Hz, 18.432–
73.728 MHz, or 90 MHz mode (see Table 15-2). The required frequency is selected by
programming the corresponding bits 16 and 17 in the System Control R egister 1
(SYSCON1) register. The sample clock (
SMPCLK)alwaysrunsattwicethefrequency
of th e shift clock (
ADCCLK).
The output channel is fed by an 8-bit shift register when the ADCCON bit of
SYSCON3isclear.WhenADCCONisset,upto16bitsofconfigurationcommandcan
be s e nt, as specified in the SYNCIO register.
The input channel is captured b y a 16-bit shift register. The clock and synchronization
pulses are activated by a write to the output shift register. During transfers the
SSIBUSY (synchronous serial interface busy) bit in the system status flags register is
set.
When the transfer is complete and valid data is in the 16-bit read shift register, the
SSEOTI interrupt in asserted and the SSIBUSY bit i s cleared. Data can then b e read
from this register location. The interrupt is cleared on the data is read from the
SYNCIO register. SSEOTI i s unmasked in the INTMR1 register an d the status is read
in the I NTSR1 register.
An additional sample cl ock (
SMPCLK) can be enabled indep endently and is set at
twice the transfer c lock frequency.
This interface has no local buffering capability and is only intended to be used with
low bandwidth interfaces, such as an ADC for a touch screen interface.
Table 15-2: ADC Interface Operation Frequencies
SYSCON1
bit 17
SYSCON1
bit 16
13.0 MHz Operation
ADCCLK Frequency
(kHz)
18.432–73.728 MHz
Operation ADCCLK
Frequency (kHz)
90.3168 MHz
Operation ADCCLK
Frequency (kHz)
0 0 4.2 4 4.9
0 1 16.9 16 19.6
1 0 67.7 64 78.4
1 1 135.4 128 156.8