User Manual

14-4 EP7309/11/12 User’s Manual - DS508UM4
Copyright Cirrus Logic, Inc. 2003
JTAG Interface
14
state will produce the correct freque ncies as shown in Table 14-3. Any other
combinations are for testing the oscillator and PLL and should not be used in-circuit.
Debug/ICE Test Mode
This mode is selected by nTEST0 =0,nTEST1 =0,LatchednURESET =1.
Selection of this mode enables the debug mode of the ARM720T. B y default, this is
disab led which saves approximately 3% on power.
Hi-Z (System) Test Mode
This mode s elected by nTEST0 =0,nTEST1 =0,LatchednURESET =0.
This test mode asynchronously disables all output buffers on the EP73xx. This has the
effect of removing the EP73xx from the PCB so that other devices on the PCB can be
in-circuit tested. The internal state of the EP73xx is not altered directly by this test
mode.
Software Selectable Test Functionality
When bit 11 of the SYSCON register is set high, inter nal peripheral bus register
accesses are output on the main address and data buses as though they were external
accesses to th e address space addressed b y
nCS[5].Hence,nCS[5] takes on a dual role,
it will be ac tive as the strobe for internal accesses and for any accesses to th e standard
address range for
nCS[5]. A dditionally, in this mode, the internal signals shown in
Table 14-4 are multiplexed out of the device on port pins.
Table 14-3: Oscillator and PLL Test Mode Signals
Signal I/O Pin Function
TSEL I PA5 PLL test mode
XTLON I PA4 Enable to oscillator circuit
PLLON I PA3 Enable to PLL circuit
PLLBP I PA0 Bypasses PLL
RTCCLK O COL0 Output of RTC oscillator
CLK1 O COL1 1 Hz clock from RTC divider chain
OSC36 O COL2 36 MHz divided PLL main clock
CLK576K O COL4 576 kHz divided from above
VREF O COL6 Test clock output for PLL
Table 14-4: Software Selectable Test Functionality
Signal I/O Pin Function
CLK O PE0 Waited clock to CPU
nFIQ O PE1 nFIQ interrupt to CPU
nIRQ O PE2 nIRQ interrupt to CPU