User Manual

EP7309/11/12 User’s Manual - DS508UM4 14-3
Copyright Cirrus Logic, Inc. 2003
JTAG Interface
1414
14
Debug Modes
The EP73xx supports a num ber of h ardware activated test modes, these are ac tivated
by the pin combinations shown in Table 14-2. All latched signals will only alter test
modes while
nPOR is low, their state is latched on the rising edge of nPOR.This
allows these signal s to be used normally during various test modes.
Within each test mode, a selection of pins is used as multiplexed outputs or inputs to
provide/monitor the test signal s unique to that mode.
Oscillator and PLL Bypass Mode
This mode is selected by nTEST0 =1,nTEST1 =0.
In th is mode, all the internal oscillators and PLL are di sabled, and the appropriate
crystal oscillator pins become the direct external oscillator inputs bypassing the
oscillator and PLL.
MOSCIN must be driven by a 36.864 MHz clock s ource and RTCIN
by a 32.768 kHz source.
Oscillator and PLL Test Mode
This mode is selected by nTEST0 =0,nTEST1 =1,LatchednURESET =0
This test mode will enable the main oscillator and will output various buffered clock
and test signals derived from the main oscillator, PLL, and 32 kHz oscillator. All
internal logic in the EP73xx will be static and isolated from the oscillators, with the
exception of the 6-bit ripple counter used to generate 576 kHz and the Real Time
Clock divide chain. Port A is used to drive the inputs of the PLL directly, and the
variousclockandPLLoutputsaremonitoredontheCOLpins.Table 14-3 defines the
EP73xx signal pins used in this test mode. This mode is only intended to allow test of
the oscillators and PLL. Note that these inputs are inverted before bei ng passed to th e
PLL to ensure that the default s tate of the p ort (all zero) maps onto the correct default
state of the PLL (TSEL = 1, X TALON = 1, PLLON = 1, D0 = 0, D1 = 1, P LLBP = 0). This
Table 14-2: EP73xx Hardware Test Modes
Test Mode
Latched
nMEDCHG
Latched
PE[0]
Latched
PE[1]
Latched
nURESET
nTEST[0] nTEST[1]
Normal operation
(32-bit boot)
100X11
Normal operation
(8-bit boot)
110X11
Normal operation
(16-bit boot)
101X11
13 MHz divided by 4 1 1 1 X 1 1
Alternative test ROM boot 0 X X X 1 1
Oscillator / PLL bypass X X X X 1 0
Functional Test (EPB) 0 X X 1 0 1
Oscillator / PLL test mode X X X 0 0 1
ICE Mode X X X 1 0 0
System test (all HiZ) X X X 0 0 0