EP73xx User’s Guide http://www.cirrus.com Copyright Cirrus Logic, Inc.
EP73xx User’s Guide Change Control Log 22 Jan 2004 Reason for entry The Users Guide has changed from Revision 3 (UM3) to Revision 4 (UM4). Significant Changes: 1. Typographical errors corrected. 2. Manual adapted for 90 MHz operation. 3. Crystal and PLL precision increased to 4 decimal points where applicable. 4. Distinction between 18-74 MHz (PLL) “mode” and precise “operation” frequency made. Example, at 90.
EP7309/11/12 User’s Manual - DS508UM4 Copyright Cirrus Logic, Inc.
1Contents Table of Contents Chapter 1. Introduction Overview ............................................................................................................................................................ 1-1 Processor ..................................................................................................................................................... 1-1 Peripherals ..................................................................................................................
Contents Timer Register Descriptions............................................................................................................................ 3-3 Timer Counter 1 Data Register (TC1D)..............................................................................................3-3 Timer Counter 2 Data Register(TC2D)...............................................................................................3-3 Real Time Clock Data Register (RTCDR) ........................................
Contents Chapter 6. Processor Support Introduction ....................................................................................................................................................... 6-1 Features .............................................................................................................................................................. 6-1 Operational Overview................................................................................................................
Contents Chapter 11. General Purpose I/O (GPIO) Introduction ..................................................................................................................................................... 11-1 Features ............................................................................................................................................................ 11-1 General Purpose I/O (GPIO) Register List ...................................................................................
Contents Operational Overview.................................................................................................................................... 16-3 DAI/CODEC/SSI2 MUX ....................................................................................................................... 16-3 DAI Interface ............................................................................................................................................ 16-4 Master/Slave SSI2 Interface ............
Contents This page intentionally blank. viii Copyright Cirrus Logic, Inc.
List of Figures Figure 1-1. EP73xx Block Diagram ............................................................................................................... 1-11 Figure 1-2. Typical EP73xx System Block Diagram ................................................................................... 1-12 Figure 2-1. ARM720T Block Diagram ............................................................................................................ 2-2 Figure 2-2. ARM720T Cache Organization .......................
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List of Tables Table 1-1: EP73xx Memory Map in External Boot Mode ............................................................................ 1-2 Table 1-2: EP73xx Internal Registers (Little Endian Mode) ........................................................................ 1-4 Table 1-3: EP73xx Internal Registers (Big Endian Mode)............................................................................ 1-6 Table 1-4: External Signal Functions ..........................................................
Table 16-6: Programmable Audio Divisors at 90 MHz ............................................................................. 16-6 Table 17-1: UART and SIR Encoder Registers ............................................................................................ 17-1 Table 17-2: UART Bit Rates at 90 MHz ........................................................................................................ 17-2 Table 17-3: UART Bit Rate in PLL Clock Mode (74 MHz) ......................................
EP7309/11/12 User’s Manual - DS508UM4 Copyright Cirrus Logic, Inc.
1Introduction 11 Chapter 1 1 Overview This chapter describes the EP73xx ARM processor, memory map, registers, and signals. See the data sheet that is associated with a specific EP73xx device for more information about pin assignments for that product. Processor The EP73xx incorporates an ARM 32-bit RISC micro controller that controls a wide range of on-chip peripherals. The ARM720T includes a a 8 Kbytes unified cache and a MMU compatible with operating systems like Windows® CE and Linux®.
Introduction • Two 16-bit general purpose timer counters • 32-bit RTC (Real-Time-Clock) timer and comparator • Dedicated LED flasher pin driven from the RTC with programmable duty ratio (Multiplexed with GPIO pin) 1 • Two synchronous serial interfaces for Micro-wire or SPI interfaces such as ADCs, one supporting both the master and slave and other supporting only master mode.
Introduction 11 Table 1-1: EP73xx Memory Map in External Boot Mode (Continued) Address Contents Size 0x8000.4000 Unused ~1 Gbyte 0x8000.0000 Internal registers 8 Kbytes 0x7000.0000 Boot ROM (nCS[7]) 128 bytes 0x6000.0000 SRAM (nCS[6]) 48 Kbytes 0x5000.0000 Expansion (nCS[5]) 256 Mbytes 0x4000.0000 Expansion (nCS[4]) 256 Mbytes 0x3000.0000 Expansion (nCS[3]) 256 Mbytes 0x2000.0000 Expansion (nCS[2]) 256 Mbytes 0x1000.0000 ROM Bank 1 (nCS[1]) 256 Mbytes 0x0000.
Introduction Note: All byte-wide registers should be accessed as words (except Port A to Port D registers, which are designed to work in both word and byte modes). All registers bit alignment starts from the LSB of the register (i.e., they are all right shift justified). The registers which interact with the 32 kHz clock or which could change during readback (i.e.
Introduction Address Name Default RD/WR Size Comments Page 0x8000.0540 PALLSW 0 RW 32 Least significant 32-bit word of LCD palette register page 9-8 0x8000.0580 PALMSW 0 RW 32 Most significant 32-bit word of LCD palette register page 9-8 0x8000.05C0 STFCLR — WR — Write to clear all start up reason flags page 5-13 0x8000.0600 BLEOI — WR — Write to clear battery low interrupt page 4-13 0x8000.0640 MCEOI — WR — Write to clear media changed interrupt page 4-13 0x8000.
Introduction Table 1-2: EP73xx Internal Registers (Little Endian Mode) (Continued) 1 Address Name 0x8000.22C0 LEDFLSH 0 RW 7 LED Flash register page 13-2 0x8000.2300 SDCONF 2 RW 32 SDRAM Configuration Register page 7-3 0x8000.2340 SDRFPR 128 RW 16 SDRAM Refresh Register page 7-4 0x8000.2440 UNIQID 0 R 32 32-bit unique ID for the EP73xx device page 5-13 0x8000.2600 DAI64Fs 0 RW 32 DAI 64Fs Control Register page 16-11 0x8000.
Introduction 11 External Signal Functions Table 1-4: External Signal Functions Function Signal Name Signal Data bus D[0-31] I/O 32-bit system data bus for memory, SDRAM, and I/O interface A[0-31] O 32 bits of system byte address during memory and expansion cycles A[27-13]/ DRA[0-14] O DRA[0-14] are multiplexed with A[27-13] for SDRAM memory accesses. A27 corresponds to DRA0 on SDRAM device.
Introduction Table 1-4: External Signal Functions (Continued) Function Signal Name Signal Description External Clock EXPCLK I/O Expansion clock rate is the same as the CPU clock for 13 MHz and 18 MHz. It runs at 36.864 MHz for 36,49 and 74 MHz modes; in 13 MHz mode this pin is used as the clock input. 1 Interrupts Power Management nMEDCHG/ nBROM I Media changed input; active low, deglitched. Used as a general purpose FIQ interrupt during normal operation.
Introduction 11 Table 1-4: External Signal Functions (Continued) Function ADC Interface (SSI1) IrDA and RS232 Interfaces LCD Keyboard & Buzzer drive LED Flasher General Purpose I/O PWM Drives Signal Name Signal Description ADCCLK O Serial clock output nADCCS O Chip select for ADC interface ADCOUT O Serial data output ADCIN I Serial data input SMPCLK O Sample clock output LEDDRV O Infrared LED drive output (UART1) PHDIN I Photo diode input (UART1) TXD[1-2] O RS232 UART1 and
Introduction Table 1-4: External Signal Functions (Continued) Function 1 Boundary Scan Test Signal Name Signal Description TDI I JTAG data in TDO O JTAG data out TMS I JTAG mode select TCLK I JTAG clock nTRST I JTAG async reset nTEST[0-1] I Test mode select inputs. These pins are used in conjunction with the power-on latched state of nURESET to select between the various device test models. MOSCIN MOSCOUT I O Main 3.6864 MHz oscillator for 18.432 MHz–90.
Introduction 11 Block Diagrams 13-MHz INPUT 3.6864 MHz INTERNAL DATA BUS PLL D[0-31] ARM720T 32.768 kHz MEMORY CONTROLLER 32.
Introduction 1 CRYSTAL MOSCIN DD[0-3] CRYSTAL RTCIN nCS[4] PB0 EXPCLK CL1 CL2 FRM M LCD COL[0-7] PC CARD CONTROLLER PC CARD SOCKET KEYBOARD D[0-31] A[0-27] PA[0-7] PB[0-7] nMOE WRITE PD[0-7] SDRAS/ SDCAS ×16 SDRAM ×16 SDRAM SDCS[0] ×16 SDRAM ×16 SDRAM SDCS[1] SDQM[0-3] SDQM[0-3] EP73XX PE[0-2] POWER SUPPLY UNIT AND COMPARATORS nPOR nPWRFL BATOK nEXTPWR nBATCHG RUN WAKEUP BATTERY DRIVE[0-1] DC-TO-DC CONVERTERS FB[0-1] nCS[0] nCS[1] ×16 FLASH ×16 FLASH SSICLK SSITXFR SSITXDA
2CPU Core 22 Chapter 2 2 Introduction The 7312 processor utilizes the ARM720T which is based on the ARM7TDMI RISC (Reduced Instruction Set Computer) core running at a dynamically programmable speed from 18-90 MHz. This chapter discusses the key features of the ARM core. Features Key features include: • ARM7TDMI CPU core (which supports the logic for the Thumb instruction set, core debug, enhanced multiplier, JTAG, and the Embedded ICE) running at a dynamically programmable clock speeds.
CPU Core Block Diagram Detailed block diagram of the core is shown below. 2 V ir tu a l A d d re s s B u s MMU 8 K by te C a c h e A R M 7 TD M I CPU C o p ro ce sso r In te rfa ce In te rn a l D a ta B u s W rite B u ffe r JT A G D ebug In te rfa ce S y ste m C o n tro l C o p ro ce sso r A M BA In te rfa ce A M BA a d d re ss AM BA d a ta Figure 2-1. ARM720T Block Diagram Programming Examples ;***************************************************************************** ; Set up the MMU.
CPU Core 22 ; ldr mcr ; r0, =0x55555555 p15, 0, r0, c3, c0 ; co-processor register c3 ;***************************************************************************** 2 ; Tell the MMU where to find the page table. ;***************************************************************************** ; IMPORT PageTable ldr r0, =PageTable mcr p15, 0, r0, c2, c0 ; co-processor register c2 ; ;***************************************************************************** ; Enable the MMU.
CPU Core Operational Overview Using the Von Neumann (load/store) architecture, the ARM720T core has a three stage instruction pipeline to increase the speed of the instruction execution within the processor. The fetch-decode-execute of concurrent instructions are done in parallel requiring approximately 1.9 CPI (cycles per instruction). 2 The core provides a 8 Kbytes unified cache and a memory management unit (MMU).
CPU Core The TLB (Translation look-aside Buffer) is a 64-entry associative cache of recent virtual address to physical address translations to eliminate a two-stage search for a higher proportion of internal register or external bus accesses. • Provides the translation and access permission information for memory accesses • For a TLB miss, the TLB walking hardware accesses the transition table from physical memory to update itself (two-stage). • If the TLB is full, a stored value will be over-written.
CPU Core 31 11 10 4 3 2 1 0 v irtu a l a d d re ss 2 by te a d d re sse s ta g R A M ta g R A M ta g R A M [1:0] ta g R A M [8:2] D a ta R A M [10:0] 1 2 8 e n try 1 2 8 en try 1 2 8 e n try 1 2 8 e n try =? =? =? =? [10:9] 2 0 4 8 x 3 2 -b it w o rd e n co d e h it d a ta Figure 2-2. ARM720T Cache Organization Cache is direct-mapped. The copy of the address or data is stored along with an address tag that is compared with the location in system memory.
CPU Core JTAG (Joint Test Action Group) or IEEE 1149 provides a boundary scan test interface with 5 dedicated signals connected directory to the CPU core: 2 • TRST - Test Reset (active low) • TCK - Test Clock • TMS - Test Mode Select • TDI - Test Data In • TDO - Test Data Out See Chapter 14 for more information on debugging the EP73xx via the JTAG interface. CPU Register Definitions ARM has 37 32-bit internal registers.
CPU Core U se r F IQ IR Q SV C U nd ef A bo r t r0 2 r1 r2 r3 r4 Banked T h u m b s ta te L ow r e g iste rs r5 r6 Banked B a n k ed B anked Banked r7 r8 r8 r9 r9 r1 0 r1 0 r1 1 r1 1 r1 2 r1 2 r 1 3 (s p ) r 1 3 (sp ) r 1 3 (s p ) r1 3 (sp ) r1 3 (sp ) r 1 3 (sp ) r 1 4 (lr ) r 1 4 (lr) r 1 4 (lr ) r1 4 (lr ) r1 4 (lr) r 1 4 (lr) sp s r sp s r s p sr s p sr sp sr T h u m b s ta te H ig h re g is te r s r1 5 (p c) c p sr Figure 2-3.
CPU Core 22 Table 2-2: ARM720T Core Coprocessor Registers Register Description 0 ID Register (Read/Write) register than may return an ID consisting of an architecture version and ARM trademark 1 Control (Read/Write) register to enable MMU, cache, write buffer, and other coprocessor operations 2 Translation Base Table (Read/Write) register contains the start address of the first level translation table 3 Domain Access Control (Read/Write) register specifies permissions for all 16 domains 4 Reser
CPU Core • Start-up resistor is not necessary. One is provided internally. • Start-up capacitors may be placed on each side of the external crystal and ground. Value for each should be around 10 pF but also should be selected based upon crystal specifications. Capacitance of the traces and crystal leads should be subtracted from the load capacitor value for precision. 2 • The crystal should have a maximum of 5 ppm frequency drift over the chips’s operating temperature range.
CPU Core 22 internal PLL clock so adjustments and consideration will need to be taken into account. PLL Equation: (PLL Multiplier/2)* 3.686 MHz = PLL Frequency ex. For 90 MHz operation, PLL Multiplier = 49 It should be noted that using the PLL Multiplier to achieve 90 MHz operation will result in a shifting up of frequencies and rates derived from the PLL by 22.5%. For example, the data bus will move from 36 MHz to 45 MHz. Take care when using a PLL-derived system because such shifting may be in effect.
CPU Core internal PLL is not used. The default value “00” for the PLL setting in SYSCON3 must not change. 2 CPU State Control There are three principal power management states on the EP73xx processor • Operating State (highest power consumption) • Idle State • Standby State (lowest power consumption) Interrupt or rising wakeup Standby Operating Write to standby location, power fail, or user reset rr te In nPOR, power fail, or user reset t up Idle Write to halt location Figure 2-4.
CPU Core • RTC remains on. Entering standby state can be accomplished in software by writing to the STDBY register, or in hardware with input from the nURESET or by nPWRFL. Before entering the standby state, the software must properly disable the DAI. Failing to do so will result in higher than expected power consumption while in this state as well as unpredictable behavior of the DAI. During standby state, all system memory and state are maintained and the system time is kept up-to-date.
CPU Core The following register will allow the system software to put the processor into Idle state. Enter the Idle State Register (HALT) 2 Address: 0x8000.0800, Write Only Definition: A write to this location will put the system into the Idle State by halting the clock to the processor until an interrupt is generated.
CPU Core 3. After nPOR goes high, the WAKEUP signal will be detected by the processor after one to two seconds. After such time, the WAKEUP (active high) signal can be detected but must be asserted high for a minimum of 125 µs Note: IMPORTANT. nURESET must not be asserted during the period between WAKEUP assertion and transition from Standby to Operating state. This will cause the processor to enter an unknown state and require a system reset to clear this condition. 4.
CPU Core 2 This page intentionally blank. 2-16 Copyright Cirrus Logic, Inc.
3Timers 33 Chapter 3 3 Introduction EP73xx has three general purpose timers that can serve as watchdogs for system resources or and events. Two timers are based on the internal PLL or 13 MHz clock and the third is fed by the RTC. Routines requiring periodic service to check status and new values can make use of these timers.
Timers str ldr str ldr str ; 3 r1, r1, r1, r0, r0, [r12, #0x0100] ; Prescale - 2 kHz clock =TC1Timer [r12, #0x300] ; 10 ms timer rate =TC1Mask [r12,#0x0280] ; Interrupt enabled Operational Overview These identical count-down timers derive their clock from the internal PLL or external 13 MHz clock. Values for these timers are programmed into the read/write registers as seen below and are decremented on the second active edge of the clock once the write to the register is complete (i.e.
Timers 33 Prescale Mode Any value written to TC1 or TC2 is automatically re-loaded when the counter underflows. Any value written to TC1 or TC2 will be decremented on the second edge of the selected clock. Setting bit 4 or 6 in SYSCON1 for TC1 and TC2 respectively, will initiate prescale mode. 3 RTC Timer The RTC timer is derived from the RTC clock. The timer interface creates a 1 Hz tick that can be controlled by the RTCDR (RTC data register).
Timers Real Time Clock Match Register (RTCMR) 3 3-4 Address: 0x8000.03C0, Read/Write Definition: The Real Time Clock match register is a 32-bit read/write register, which sets and reads the binary match time to RTC. Any value written will be compared to the current binary time in the RTC, if they match it will assert the RTCMI interrupt source. This register is reset only by nPOR. Copyright Cirrus Logic, Inc.
4Interrupt Controller 44 Chapter 4 4 Introduction Like most modern microprocessors, the EP73xx contains an interrupt controller to manage both external and internal exceptions. When an expected or unexpected event arises during the execution of a program (i.e. interrupt or memory fault) an exception is generated. If more than one exception occurs at the same time, a fixed priority system determines the order in which they are handled.
Interrupt Controller Table 4-1: Interrupt Registers (Continued) 4 Address Name Type Size Description Page 0x8000.07C0 COEOI R/W --- CODEC EOI page 4-14 0x8000.1700 KBDEOI R/W --- Keyboard EOI page 4-14 0x8000.
Interrupt Controller 44 bne mov strb mov str nextstatuscheck ; not the timer - moving down the IRQ routine r2, #0x0 r2, [r0,#0x0] ; setting PA0-8 low r2, #0xFFFFFFFF r2, [r0,0x06C0] ; Write to TC1EOI register - clear interrupt 4 ; ........ code........... subs ; pc, lr, #4 ; Return from interrupt to pending instruction Operational Overview Once an exception occurs, the ARM720T will attempt to complete the current instruction (except for a system reset) and will then identify the interrupt type.
Interrupt Controller Interrupt Types and Priorities The EP73xx interrupt controller can generate two types of interrupts: Standard (IRQ) or Fast (FIQ). Seventeen of the twenty-two interrupt sources are IRQ interrupts, while the remaining five are FIQ. FIQs have a higher priority than IRQs. If two interrupts are received from within the same group (IRQ or FIQ), the order in which they are serviced must be resolved in software. The priorities are listed in Table 4-3.
Interrupt Controller Table 4-4, Table 4-5, and Table 4-6 show the names and allocation of interrupts in the EP73xx.
Interrupt Controller Interrupt Latencies in Different States Operating State The ARM720T processor checks for a low level on its FIQ and IRQ inputs at the end of each instruction. The interrupt latency is therefore directly related to the amount of time it takes to complete execution of the current instruction when the interrupt condition is detected. There is a one to two clock cycle synchronization penalty following the assertion of the interrupt.
Interrupt Controller The Standby State equates to the system being switched “off” (i.e., no display, and the main oscillator is shut down). If the 18.432–73.72 MHz mode is selected, the PLL will be shut down. In the 13 MHz mode, if the CLKENSL bit is set low, the CLKEN signal will be forced low and can, if required, be used to disable an external oscillator. In Standby State, all system memory and state is maintained and system time is kept current.
Interrupt Controller Interrupt Register Descriptions Interrupt Status Register 1 (INTSR1) 4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSEOTI UMSINT URXINT1 UTXINT1 TINT RTCMI TC2OI TC1OI EINT3 EINT2 EINT1 CSINT MCINT WEINT BLINT EXTFIQ Address: 0x8000.0240, Read Only Definition: The interrupt status register is a 32-bit read only register.
Interrupt Controller Media changed interrupt. This interrupt will be active after a rising edge on the nMEDCHG input pin has been detected, This input is de-glitched with a 16 kHz clock so it will only generate an interrupt if it is active for longer than 125 µs. It is mapped to the FIQ input on the ARM7TDMI processor and is cleared by writing to the MCEOI location.
Interrupt Controller UTXINT1: Internal UART1 transmit FIFO half-empty interrupt. The function of this interrupt source depends on whether the UART1 FIFO is enabled. If the FIFO is disabled (FIFOEN bit is clear in the UART1 bit rate and line control register), this interrupt will be active when there is no data in the UART1 TX data holding register and be cleared by writing to the UART1 data register.
Interrupt Controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 SS2TX SS2RX KBDINT RSVD 15 14 RSVD 13 12 URXINT2 UTXINT2 11 10 9 8 RSVD Address: 0x8000.1240, Read / Write Definition: This register is an extension of INTSR1. This interrupt status register also reflects the current state of the new interrupt sources within the EP73xx. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given below.
Interrupt Controller URXINT2: UART2 receive FIFO half full interrupt. The function of this interrupt source depends on whether the UART2 FIFO is enabled. If the FIFO is disabled, this interrupt will be active when there is valid RX data in the UART2 RX data holding register and be cleared by reading this data.
Interrupt Controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSVD DAIINT Address: 0x8000.2280, Read / Write Definition: This register contains the interrupt mask for the DAI interface. This interrupt triggers the fast interrupt (FIQ) signal of the ARM720T core. Bit Descriptions: DAIINT: DAI interface interrupt. The cause must be determined by reading the DAI status register.
Interrupt Controller TC1 End of Interrupt (TC2EOI) 4 Address: 0x8000.0700 Definition: A write to this location will clear the under flow interrupt generated by TC2. RTC Match End of Interrupt (RTCEOI) Address: 0x8000.0740 Definition: A write to this location will clear the RTC match interrupt. UART1 Modem Status Changed End of Interrupt (UMSEOI) Address: 0x8000.0780 Definition: A write to this location will clear the modem status changed interrupt.
5System Registers 55 Chapter 5 5 Introduction The SYSCON and SYSFLG registers control and report the status of the various components of the EP73xx system-on-chip device. There are three read/write SYSCON system configuration registers, and two SYSFLG read only system flag registers.
System Registers System Register List Table 5-1: System Registers 5 Address Name Type Size Description Page 0x8000.0100 SYSCON1 R/W 32 System Control Register 1 page 5-4 0x8000.1100 SYSCON2 R/W 16 System Control Register 2 page 5-7 0x8000.2200 SYSCON3 R/W 16 System Control Register 3 page 5-8 0x8000.0140 SYSFLG1 Read 32 System Status Flag Register page 5-9 0x8000.1140 SYSFLG2 Read 32 System Status Flag Register page 5-12 0x8000.
System Registers 55 Operational Overview Most of the functions represented in the SYSCON and SYSFLG registers are either described thoroughly in other chapters or require little explanation. Below is a detailed explanation of those that do not get covered sufficiently elsewhere in this manual. 5 Buzzer The BUZ output pin on the EP73xx is intended as a signal source for a basic annunciator. Two hardware sources and one software source are available for controlling the frequency of the signal.
System Registers MaverickKey™ Unique-ID MaverickKey registers are unique ID numbers that are programmed for use in secure web content and commerce. These IDs, burned into specific register locations give the OEMs a method for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. 5 There is a single 32-bit Unique ID as well as a 128-bit random ID and are laser programmed at the factory.
System Registers 55 Table 5-2: Keyboard Column Drive State (Continued) Value Column Drive State 11 Column 3 high, all others Hi-Z 12 Column 4 high, all others Hi-Z 13 Column 5 high, all others Hi-Z 14 Column 6 high, all others Hi-Z 15 Column 7 high, all others Hi-Z 5 TC1M: Timer counter 1 mode. Setting this bit sets TC1 clock to prescale mode, clearing it sets free running mode. TC1S: Timer counter 1 clock source.
System Registers ADCKSEL: Microwire/SPI peripheral clock speed select. This two bit field selects the frequency of the ADC sample clock, which is twice the frequency of the synchronous serial ADC interface clock. The table below shows the available frequencies for operation when the CPU is operated in either PLL mode or in 13 MHz external clock mode. These bits are also used to select the master mode shift clock frequency for the SSI2 interface when set into master mode.
System Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 SS2TXE N KBWEN SDRAM Z KBD6 SERSEL RSVD 15 14 13 12 RSVD BUZFRE Q CLKEN SL OSTB 11 10 RSVD 9 8 7 SS2MA EN UART2E N SS2RXE N RSVD 5 Address: 0x8000.1100, Read / Write Definition: The SYSCON2 system control register is a 15-bit read/write register which controls some of the general configuration parameters for the EP73xx as well as the control and status of internal peripherals.
System Registers SS2MAEN: Master mode enable for the synchronous serial interface 2. When low, SSI2 will be configured for slave mode operation. When high, SSI2 will be configured for master mode operation. This bit also controls the directionality of the interface pins. OSTB: 5 This bit (operating system timing bit) is for use only with the 13 MHz clock source mode.
System Registers 55 Table 5-4: ARM720T Clock Speed Settings CLKCTL[1-0] Value Processor Frequency Memory Bus Frequency Wait State Scaling 00 18.432 MHz 18.432 MHz 1 01 36.864 MHz 36.864 MHz 2 10 49.152 MHz 36.864 MHz 2 11 73.728 MHz 36.864 MHz 2 5 Refer to the Expansion Bus Controller chapter for explicit details on programmed wait states at different bus frequencies. DAISEL: When set, selects the DAI interface. When cleared, selects the SSI interface.
System Registers Bit Descriptions: MCDR: Media changed direct read. This bit reflects the inverted, nonlatched status of the media changed input. DCDET: This bit will be set if a non-battery operated power supply is powering the system (it is the inverted state of the nEXTPWR input pin). WUDR: Wake up direct read. This bit reflects the non-latched state of the wakeup signal. WUON: This bit will be set if the system has been brought out of the Standby State by a rising edge on the wakeup signal.
System Registers UART1 receiver FIFO empty. The meaning of this bit depends on the state of the UFIFOEN bit in the UART1 bit rate and line control register. If the FIFO is disabled, this bit will be set when the RX holding register is empty. If the FIFO is enabled, the URXFE bit will be set when the RX FIFO is empty. UTXFF1: UART1 transmit FIFO full. The meaning of this bit depends on the state of the UFIFOEN bit in the UART1 bit rate and line control register.
System Registers System Flag Register 2 (SYSFLG2) 31 30 29 28 27 26 25 24 RSVD 5 15 14 13 RSVD 12 11 10 UBUSY 2 9 8 23 22 UTXFF2 URXFE2 7 6 5 4 CKMOD E SS2TXU F SS2TXF F RSVD 21 20 19 18 17 16 3 2 1 0 SS2RXF E RESFR M RESVAL SS2RX OF RSVD Address: 0x8000.1140, Read Only Definition: The SYSFLG2 system flag register is a 32-bit read only register. It provides information regarding the status of the CPU and associated peripherals.
System Registers UART2 receiver FIFO empty. The meaning of this bit depends on the state of the UFIFOEN bit in the UART2 bit rate and line control register. If the FIFO is disabled, this bit will be set when the RX holding register contains is empty. If the FIFO is enabled, the URXFE bit will be set when the RX FIFO is empty. UTXFF2: UART2 transmit FIFO full. The meaning of this bit depends on the state of the UFIFOEN bit in the UART2 bit rate and line control register.
System Registers 5 This page intentionally blank. 5-14 Copyright Cirrus Logic, Inc.
6Processor Support 66 Chapter 6 6 Introduction The EP73xx processor has an internal and external boot mode. In each instance, the processor will fetch from ROM memory, either internal or external ROM respectively. The processor, in either mode, can be configured to interface with a big or little endian device.
Processor Support Internal Boot Mode The 128 bytes of on-chip Boot ROM contain an instruction sequence that configure UART1 to receive up to 2 Kbytes of serial data which is then placed in the on-chip SRAM. Once the download is complete, the program counter jumps to SRAM to begin executing the downloaded data. The purpose of this mode is to allow the downloaded code to facilitate programming of FLASH or other ROM device. See Appendix A for code details.
Processor Support Table 6-3: Memory Map in External Boot Mode Address Contents Size 0xF000.0000 Reserved 256 Mbytes 0xE000.0000 Reserved 256 Mbytes 0xD000.0000 Reserved 256 Mbytes 0xC000.0000 SDRAM 64 Mbytes 0x8000.4000 Unused ~1 Gbyte 0x8000.0000 Internal registers 16 Kbytes 0x7000.0000 Boot ROM (nCS[7]) 128 bytes 0x6000.0000 SRAM (nCS[6]) 48,400 bytes 0x5000.0000 Expansion (nCS[5]) 256 Mbytes 0x4000.0000 Expansion (nCS[4]) 256 Mbytes 0x3000.
Processor Support Endianess The EP73xx uses little endian configuration for the internal registers. However, it is possible to connect to a big endian external memory device. The big-endian/littleendian bit in the internal registers sets whether the EP73xx treats words in memory as being stored in big endian or little endian format.
Processor Support 66 Table 6-5: Effect on Endianess on Write Operations (Continued) Byte Lanes to Memory / Ports / Registers Address (W/B) Register Contents Big Endian Memory Little Endian Memory 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 Word + 2 (H) 11223344 44 33 44 33 44 33 44 33 Word + 3 (H) 11223344 44 33 44 33 44 33 44 33 Word + 0 (B) 11223344 44 44 44 44 44 44 44 44 Word + 1 (B) 11223344 44 44 44 44 44 44 44 44 Word + 2 (B) 11223344 44 44 44
Processor Support 6 This page intentionally blank. 6-6 Copyright Cirrus Logic, Inc.
7SDRAM Controller 77 Chapter 7 7 Introduction External SDRAM on the EP7311 and EP7312 is supported via the SDRAM controller. It allows industry standard SDRAM memories to be used within the address space of the EP73xx with no software overhead. The controller is attached to the ARM core through the internal high speed bus. It operates at a maximum clock speed of 36.864 MHz (45 MHz when is CPU running at 90 MHz), providing all the necessary connections to interface to two banks of SDRAM.
SDRAM Controller Programming Example ;***************************************************************************** ; Sample initialization code for the SDRAM controller on the EDB7312: ;***************************************************************************** 7 ; ldr ldr add mov str mov str ; r0,=0x80000000 ; internal registers r3,=0x2000 ; local offset for memory r4,r3,r0 ; add & store offset in r4 r1,#0x522 ; CASLAT=2, SDSIZE=64 Mb, SDWIDTH=16, CLKCTL=0, SDACTIVE=1 r1,[r4,#0x300] ; store in SDCO
SDRAM Controller 77 The SDRAM controller will continue to provide refresh cycles at the rate set in SDRFPR until the SDACTIVE bit is set to 0 or the CPU is reset. Byte Masks Pins PD6 and PD7 are multiplexed with the SDQM0 and SDQM1 signals, respectively. ENPD67, bit 10 in the SYSCON3 register, enables pins PD6 and PD7 as GPIO bits when set. This is useful in applications which do not involve the SDRAM interface.
SDRAM Controller SDWIDTH[1:0]: The width of each SDRAM device: 00 = 4 bits 01 = 8 bits 10 = 16 bits 11 = 32 bits This value is independent of the bus width setting and is necessary to differentiate the individual devices within a bank. 7 CLKCTL: Control over the SDRAM clock: 0 = SDRAM clock is permanently enabled except when in standby mode. 1 = SDRAM clock stops when the EP73xx is put into the STANDBY state or SDACTIVE = ‘0’.
8SRAM/Expansion Bus Controller 88 Chapter 8 8 Introduction The SRAM/Expansion bus controller allows for control and access to internal/external SRAM memory as well as external peripherals that require read/write access to the EP73xx memory bus. The following description will encompass both situations and detail the programming and configuration of each of bus.
SRAM/Expansion Bus Controller MemConfig1value MemConfig2value EQU EQU 0x3c011814 ; CS0-CS3 configuration values 0x0000001e ; CS6(Internal SRAM) CS7(Internal Boot ROM) ;***************************************************************************** 8 ; configure nCS0 - nCS3 ;***************************************************************************** ; ldr str ; r1, =MemConfig1value r1,[r12,#0x0180] ; MEMCFG1 = 0x8000.
SRAM/Expansion Bus Controller Memory Configuration Register 1 (MEMCFG1) 31 30 29 28 27 26 25 24 23 22 21 20 nCS[3] Configuration 15 14 13 12 19 18 17 16 8 nCS[2] Configuration 11 10 9 8 7 6 5 4 nCS[1] Configuration 3 2 1 0 nCS[0] Configuration Address: 0x8000.0180, Read / Write Definition: Each of the chip selects contain the same 8-bit programmable bit fields that make up the entire configuration.
SRAM/Expansion Bus Controller Table 8-2: Bus Width Selection Settings 8 Bus Width Field Expansion Transfer Mode Port E bits 1,0 during nPOR reset 01 32-bit wide bus access High, Low 10 Reserved High, Low 11 8-bit wide bus access High, Low Wait States Field[2:5]: There are two tables to use to program a chip select with a specific number of wait states. One table is specifically for 13 and 18 MHz operation and the other is for 36 MHz and above.
SRAM/Expansion Bus Controller CLKENB[7]: Expansion clock enable. Setting this bit enables the EXPCLK to be active during accesses to the selected expansion device. This will provide a timing reference for devices that need to extend bus cycles using the EXPRDY input. Back-to-back (but not necessarily page mode) accesses will result in a continuous clock. This bit will only affect EXPCLK when the PLL is being used (i.e., in 73.72818.432 MHz mode.
SRAM/Expansion Bus Controller 8 This page intentionally blank. 8-6 Copyright Cirrus Logic, Inc.
9LCD Interface 99 Chapter 9 9 Introduction The LCD interface provides all the necessary control signals to interface directly to a single panel multiplexed LCD. It is programmable for different line lengths, bits-perpixel and refresh rates. The frame buffer can reside in either SDRAM and RAM memory. 1/4 VGA support is typical but 1/2 VGA (monochrome) support is possible assuming a refresh rate above 40 Hz is not required. When the CPU speed is set to 74 MHz, the bus speed will be 36 MHz.
LCD Interface Programming Example ;************************************************************************ ; LCD Controller Configuration for a 640x240x4 bpp LCD Panel (ALPS) ; AC Prescale = 0x18 (LCD Manufacturer Number) ; Refresh Rate = 60 Hz ; LCD Palettes require 1 to 1 mapping between pixel value to intensity ; Pixel Prescale = 3 9 ;************************************************************************ ; LCDCON EQU 0xF01CF2BF ; Value for LCDCON register for above req.
LCD Interface The screen is mapped as on contiguous block of memory where each horizontal line of pixels is mapped to a set of consecutive bytes or words. Pixel 0 represent the LSB in a word wide access of the frame buffer memory consistent with little endian configuration. LCD DMA Controller The DMA controller for the LCD controller is dedicated to the controller and is designed to fetch from the frame buffer memory and fill a nine-word deep FIFO.
LCD Interface Latency and access times will need to be calculated prior to selecting an LCD panel to guarantee available bandwidth for the rest of the system. It should be noted that the refresh rate is not affected by the total number of pixels. 9 Gray Scale The figure below shows the organization of the video map for all bits-per-pixel combinations. As seen the in the diagram, the gray scale blocks represent the two 32bit palette registers.
LCD Interface 99 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Gray scale 9 Gray scale Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 4 Bits per pixel Pixel 1 Pixel 2 Pixel 3 Pixel 4 Gray scale Gray scale Bit 0 Gray scale Bit 1 Bit 2 Bit 3 Bit 4 Gray scale Bit 5 Bit 6 Bit 7 2 Bits per pixel Pixel 1 Pixel 2 Pixel 3 Pixel 4 Gray scale Gray scale Gray scale Gray scale Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 1 Bit per pixel Figure 9-1.
LCD Interface Hardware Interface 9 DD3 1,1 DD2 1,2 DD1 1,3 DD0 1,4 1,640 640x240 LCD Screen 240,1 240,640 Figure 9-2. LCD Data to Pixel Mapping DD3-DD0 carries the data that is output from the gray scale palette registers. Data for each pixel will begin with the first nibble (assuming 4 bpp) at the beginning of the frame buffer which will correspond to the first pixel location as seen above. For 2 bpp and 1 bpp, the same hardware interface applies.
LCD Interface 99 LCD Register Descriptions LCD Control Register (LCDCON) 31 30 GSMD GSEN 15 14 29 28 27 26 25 24 23 22 AC Prescale 13 12 11 21 20 19 18 Pixel Prescale 10 Length 9 8 7 6 5 17 16 Line 4 3 2 1 0 VIdeo Buffer Size Address: 0x8000.02C0, Read / Write Bit Descriptions: Video Buffer Size [0:12]:Total number of bits in the video display buffer. Formula: (Total bits in video buffer/128) - 1 ex.
LCD Interface GSEN[30]: Gray scale enable bit. Enables gray scale output to the LCD. When cleared, each bit in the video map directly corresponds to a pixel in the display. 9 GSMD[31]: Gray scale mode bit. Clearing this bit sets the controller to 2 bpp (4-gray scale). Setting this bits enables 4 bpp (16-gray scale).
LCD Interface 99 Table 9-2: Gray Scale Value to Color Mapping Gray scale Value Duty Cycle % Pixels Lit % Step Change 0 0 0% 11.1% 1 1/9 11.1% 8.9% 2 1/5 20.0% 6.7% 3 4/15 26.7% 6.6% 4 3/9 33.3% 6.7% 5 2/5 40.0% 5.4% 6 4/9 44.4% 5.6% 7 1/2 50.0% 0.0% 8 1/2 50.0% 5.6% 9 5/9 55.6% 5.4% 10 3/5 60.0% 6.7% 11 6/9 66.7% 6.6% 12 11/15 73.3% 6.7% 13 4/5 80.0% 8.9% 14 8/9 88.9% 11.
LCD Interface 9 This page intentionally blank. 9-10 Copyright Cirrus Logic, Inc.
10Keyboard Interface Introduction The keyboard interface provides the necessary hardware for a direct connect to an 8x8 or 64-key entry keyboard. Scanning for a keypress involves column and GPIO pins which assert and read column by column. If enabled, there is an internal interrupt that be generated from a keypress. Features • Maximum direct interface of an 8x8 array • Dedicated column drives and GPIOs for detection • Keyboard interrupt (if enabled) Register List See Chapter 5.
Keyboard Interface Operational Overview The keyboard interface is made up of an 8x8 array of column drive to GPIO (port A) pins and an interrupt for a keypress. When the keyboard interrupt is enabled, all GPIO pins on port A are ORed together internally. This allows any keypress (if port A is used) to generate an interrupt when required.
Keyboard Interface • KBD6 is set: Lowest 6 bits of Port A are OR’ed together to produce the internal wakeup signal and the keyboard interrupt request. The upper two bits on port A are available as GPIOs. 1010 the default state. 10 EP7309/11/12 User’s Manual - DS508UM4 Copyright Cirrus Logic, Inc.
Keyboard Interface 10 This page intentionally blank. 10-4 Copyright Cirrus Logic, Inc.
11General Purpose I/O (GPIO) Introduction GPIOs are user controlled pins that can be configured as independent input and output data registers. Input or output data is read or written respectively to the register address. Typical uses include keyboard interface, control signal interface for external peripherals, and data transfer.
General Purpose I/O (GPIO) Programming Example ;******************************************************************* ; Enable GPIO Port B as Outputs.
12PWM Interface Introduction There are two PWM (Pulse Width Modulator) outputs. This was designed for DC to DC conversion circuits but can be used for other types of controls. Typical use includes backlight voltage for LCDs and programmable LCD contrast voltages.
PWM Interface PWM (Pulse Width Modulator) Register List Table 12-1: PWM (Pulse Width Modulator) Registers 12 Address Name Type Size Description Page 0x8000.0400 PMPCON R/W 12 Pump (PWM) Control Register page 12-3 Programming Example ;***************************************************************************** ; Example turns on PWM drive O.
PWM Interface Pump Control Register (PMPCON) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 RSVD 10 9 Drive 1 Pump Ratio 8 Drive 0 from AC Source Ratio Address: 0x8000.0400, Read / Write Default: 0x00000000 12 Drive 0 from Battery Ratio Bit Descriptions: Drive 0 from Battery Ratio[0:3]:Control of the Drive 0 PWM pump while the system is battery powered.
PWM Interface 12 This page intentionally blank. 12-4 Copyright Cirrus Logic, Inc.
13Dedicated LED Flasher Introduction LED flasher provides a user interface to toggle a specific GPIO pin for use to flash an LED or other signaling device. A benefit of this feature is that the system, regardless of the processor state, will continue to control this port. Only a system reset, loss of power, or malfunction would prevent normal operation of the LED flasher. LED Flasher Register List Table 13-1: LED Flasher Registers Address Name Type Size Description Page 0x8000.
Dedicated LED Flasher Register Definitions LED Flasher Register (LEDFLSH) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSVD 13 Address: Enable Duty Ratio Flash Rate 0x8000.22C0, Read / Write Bit Descriptions: Flash rate[0:1]:Values 1-4 determines rate in seconds Duty Ratio[2:5]: Percent duty cycle from 1/16 to 15/16 for flash rate Enable[6]: Turns flasher on. 13-2 Copyright Cirrus Logic, Inc.
14JTAG Interface Introduction EmbeddedICE® is an extension to the architecture of the ARM family of processors, and provides the ability to debug cores that are deeply embedded into systems. The processor also has built-in test modes for functional testing of system clock and other interfaces.
JTAG Interface Boundary Scan IEEE 1149.1 compliant JTAG is provided with the EP73xx. The Table 14-1 shows the instructions that are supported in the EP73xx. Table 14-1: Instructions Supported in JTAG Mode Instruction 14 Code Description EXTEST 0000 Places the selected scan chain in test mode. SCAN_N 0010 Connects the Scan Path Register between TDI and TDO SAMPLE / PRELOAD 0011 This instruction is included for product testing only and should never be used.
JTAG Interface The EP73xx supports a number of hardware activated test modes, these are activated by the pin combinations shown in Table 14-2. All latched signals will only alter test modes while nPOR is low, their state is latched on the rising edge of nPOR . This allows these signals to be used normally during various test modes. Within each test mode, a selection of pins is used as multiplexed outputs or inputs to provide/monitor the test signals unique to that mode.
JTAG Interface state will produce the correct frequencies as shown in Table 14-3. Any other combinations are for testing the oscillator and PLL and should not be used in-circuit.
JTAG Interface The “Waited clock to CPU” is an internally ANDed source that generates the actual CPU clock. Thus, it is possible to know exactly when the CPU is being clocked by viewing this pin. The signals nFIQ and nIRQ are the two output signals from the internal interrupt controller. They are input directly into the ARM720T processor. 1414 This test is not intended to be used when LCD DMA accesses are enabled.
JTAG Interface 14 This page intentionally blank. 14-6 Copyright Cirrus Logic, Inc.
15SSI Port Introduction The EP73xx provides two synchronous serial channels for use with audio devices, telephony CODECs, and other devices using SPI or Microwire like communications formats. The first of the two channels supports standard SPI and Microwire formats for interfacing with low-bandwidth devices and is always associated with the SSI1 unit. The SSI1 interface is most commonly used to communicate with an A/D convertor for digitizing pen input from a touch screen.
SSI Port CFGBYTE TXLENGTH TXEN ; ldr mov mov mov orr orr str 15 EQU EQU EQU 0x83 ; channel 1 data for ADC data request 0x18 ; transmit packet 24 bits (ADC spec0) 0x1 ; Transmit enable bit r0, =0x80000000 r2, #CFGBYTE r1, #TXLENGTH r3, #TXEN r2,r2,r1, lsl #8 r2, r2,r3, lsl #14 r2, [r0,#0x500] ; Data packet request sent to ADC for channel 1 data ; again ldr r1,[r0, #0x140] ; wait loop for SSIBUSY and r1, #0x4000000 cmp r1, #0x0 bne again ; ldr r1,[r0, #0x500] ; read first byte of data and discard str r2
SSI Port Unlike the SSI2/DAI/CODEC interface, SSI1 has a dedicated set of I/O pins and does not require an elaborate initialization procedure. The clock output frequency is programmable and only active during data transmissions to save power. There are four output frequencies selectable, which will be slightly different depending whether the device is operating in a 13 MHz, 18.432– 73.728 MHz, or 90 MHz mode (see Table 15-2).
SSI Port SSI Port Register Descriptions Synchronous Serial ADC Interface Data Register (SYNCIO) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 RSVD TXFRME N SMCKE N 15 12 11 10 9 8 Frame Length ADC Configuration Byte 0x8000.
SSI Port 1515 ADC Configuration Extension:When the ADCCON control bit in the SYSCON3 register=0, this field is N/A. ADCCON = 1, this field is the configuration data sent to the ADC. This field is determined by the value held in the ADC Configuration Length field (SYNCIO[6:0]) 15 EP7309/11/12 User’s Manual - DS508UM4 Copyright Cirrus Logic, Inc.
SSI Port 15 This page intentionally blank. 15-6 Copyright Cirrus Logic, Inc.
16DAI/CODEC/SSI2 Introduction The second channel is connected to a MUX which selects amongst the CODEC, DAI, and SSI2 interfaces. The CODEC interface is intended for use with telephony-style CODECS. High quality ADCs, DACs, or CODECs such as the Cirrus Logic CS53L32A, CS43L42, and CS42L50 are easily added to an EP7309 or EP7312 design via the DAI I2S standard interface. The SSI2 port provides an additional SPI port with Master/Slave interface control.
DAI/CODEC/SSI2 Block Diagram SSICLK SSITXFR SSITXDA SSIRXDA SSIRXFR DAI 128/64 fs CODEC SSI2 16 Figure 16-1. Portion of the EP73xx Block Diagram Showing Multiplexed Feature DAI/CODEC/SSI2 Register List Table 16-1: DAI/CODEC/SSI2 Registers Address Name Type Size Description Page 0x8000.2600 DAI64Fs R/W 16 DAI Mode Control Register page 16-11 0x8000.2000 DAIR R/W 32 DAI Control Register page 16-11 0x8000.2040 DAIR0 R/W 16 DAI Data Register 0 page 16-14 0x8000.
DAI/CODEC/SSI2 r1, =DAISEL r1, [r12, #0x100] ; Select DAI in SYSCON1 0x8000.0100 r1, =DAI64FS r11,r11,#0x1000 ; Set 0x8000.2000 base address r1, [r11, #0x600] ; Set DAI64FS 0x8000.2600 r1, [r11, #0x200] r0, #1 r1, r1, r0, lsl #9 ; Clear bit 9 in SYSCON3 for 64fs r1, [r11, #0x200] ; Set 64fs mode in SYSCON3 0x8000.2000 r1, =DAIEN r1, [r11, #0x0] ; Enable DAI at 0x8000.
DAI/CODEC/SSI2 Table 16-3: Pin Sharing for Multiplexor 16 Pin No.
DAI/CODEC/SSI2 The DAI contains a series of programmable clocks to support a wide variety of sample rates. A graphical representation of the DAI clock scheme is contained in Figure 16-2. Programmable D ivide (AUDIV ) MUX (AUDCLKS RC) 7-bit counter fixed at 4 128/64(Fs) PLL (90.3168 MHz) /2 /32 Audio Bit Clock 128/64(Fs) EX TCLK (11.2896 MHz) (12.288 MHz) Audio Sam ple Frequency Audio Data FIFO Control (F s) 16 S CLK LRCLK (Fs) /128 /64 MCLK (B UZ) Figure 16-2.
DAI/CODEC/SSI2 Table 16-6: Programmable Audio Divisors at 90 MHz Clock Source (MHz) Sample Frequency (kHz) 128 Fs Audio Bit Clock (MHz) 64 Fs Audio Bit Clock (MHz) 128/64 Fs Divisor (AUDIV) *90.3168 8 1.024 0.512 44 11.025 1.4112 0.7056 32 12.288 12 1.536 0.786 8 *90.3168 16 2.048 1.024 22 22.05 2.8224 1.4112 16 12.288 24 3.072 1.536 4 *90.3168 32 4.096 2.048 11 44.1 5.6448 2.8224 8 48 6.144 3.072 2 * 90.3168 ** 16 * 90.3168 ** * 90.3168 ** 12.
DAI/CODEC/SSI2 Master/Slave SSI2 Interface A second SPI/Microwire interface with full master/slave capability is provided by the EP73XX. Data rates in slave mode are theoretically up to 512 kbits/s, full duplex, although continuous operation at this data rate will give an interrupt rate of 2 kHz, which is too fast for many operating systems. This would require a worst-case interrupt response time of less than 0.5 ms and would cause loss of data through TX underruns and RX overruns.
DAI/CODEC/SSI2 Slave 7212 16 Master 7212 SSIRXFR SSIRXFR SSITXFR SSITXFR SSICLK SSICLK SSIRXDA SSITXDA SSITXDA SSIRXDA Figure 16-3. SSI2 Port Directions in Slave and Master Mode Data on the link is sent MSB first and coincides with an appropriate frame sync pulse, of one clock in duration, located one clock prior to the first data bit sent (i.e., MSB). It is not possible to send data LSB first.
DAI/CODEC/SSI2 Note: All the writes/reads to the FIFO are done word at a time (data on the lower 16 bits is valid and upper 16 bits are ignored). Software manually pops the residual byte into the RX FIFO by writing to the SS2POP location (the value written is ignored). This write will strobe the RX FIFO write signal, causing the residual byte to be written into the FIFO. 16 Residual bit valid 11 00 New RX byte received New RX byte received Pop FIFO 01 Figure 16-4.
DAI/CODEC/SSI2 will begin one clock, or more, after the last byte transferred and will resume at least one clock prior to the first frame sync assertion. To disable the clock, the TX section is turned off. Note: In Master mode, the EP73xx does not support the discontinuous clock. Error Conditions RX FIFO overflows are detected and conveyed via a status bit in the SYSFLG2 register. This register should be accessed at periodic intervals by the application software.
DAI/CODEC/SSI2 Data is loaded into the transmit FIFO by writing to the CODR register. At the beginning of a transmit cycle, this data is loaded into a shift/load register. Just prior to the byte being transferred out, PCMSYNC goes high for one PCMCLK cycle. Then the data is shifted out serially to PCMOUT, MSB first, (with the MSB valid at the same time PCMSYNC is asserted). Data is shifted on the rising edge of the PCMCLK output.
DAI/CODEC/SSI2 DAI Control Register (DAIR) 31 30 29 28 27 26 25 24 23 RSVD 15 14 13 12 11 10 9 8 22 21 20 19 18 17 16 RCRM RCTM LCRM LCTM RSRVD ECS DAIEN 6 5 4 3 2 1 0 7 RSVD Address: 16 0x8000.2000, Read / Write Bit Descriptions: (See full bit descriptions for complete details) [0:15]: Reserved. Must be set to 0x0404 DAIEN: DAI Interface Enable (See additional notes for more detail) 0-DAI operation disabled.
DAI/CODEC/SSI2 DAIEN: When the DAI is disabled, all of its clocks are powered down to minimize power consumption. Note that DAIEN is the only control bit within the DAI interface that is reset to a known state. It is cleared to zero to ensure the DAI timing is disabled following a reset of the device. When the DAI timing is enabled, SCLK begins to transition and the start of the first frame is signaled by driving the LRCK pin low.
DAI/CODEC/SSI2 RCTM: The Left Channel Sample Receive FIFO interrupt mask (LCRM) bit is used to mask or enable the Left Channel Receive FIFO service request interrupt. When LCRM = 0, the interrupt is masked and the state of the left channel sample receive FIFO service request (LCRS) bit within the DAI status register is ignored by the interrupt controller. When LCRM = 1, the interrupt is enabled and whenever LCRS is set (one) an interrupt request is made to the interrupt controller.
DAI/CODEC/SSI2 DAI Data Register 1 (DAIDR1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bottom Left Channel Receive FIFO / Top Left Channel Transmit FIFO Address: 0x8000.2080, Read / Write Bit Descriptions: [0:15]: Bottom Left Receive and Top Left Transmit FIFO. Data is filed and extracted from the Left Channel FIFOs using this register.
DAI/CODEC/SSI2 DAI Data Register 2 (DAIDR2) 31 30 29 28 27 26 25 24 23 22 21 20 RSVD 15 14 13 12 11 10 19 18 17 16 FIFO Channel Select 9 8 7 FIFOEN 6 5 4 3 2 1 0 RSVD 0x8000.
DAI/CODEC/SSI2 Left Channel Transmit FIFO Service Request Flag (read only) 0 - Left Channel Transmit FIFO is more than half full (five entries or more are filled) or DAI is disabled. 1- Left Channel Transmit FIFO is more than half full or less (four or fewer entries filled) and the DAI operation is enabled. LTCM = 1. LCRS: Left Channel Receive FIFO Service Request Flag (read only) 0 - Left Channel Receive FIFO is more than half full (five entries or fewer are filled) or DAI is disabled.
DAI/CODEC/SSI2 Full Bit Descriptions RCTS: The Right Channel Transmit FIFO Service Request Flag (RCTS) is a read-only bit which is set when the Right Channel Transmit FIFO is nearly empty and requires service to prevent an underrun. RCTS is set any time the Right Channel Transmit FIFO has four or fewer entries of valid data (half full or less), and is cleared when it has five or more entries of valid data.
DAI/CODEC/SSI2 RCRO: The Right Channel Receive FIFO Overrun Status Bit (RCRO) is set when the right channel receive logic attempts to place data into the Right Channel Receive FIFO after it has been completely filled. Each time a new piece of data is received, the set signal to the RCRO status bit is asserted, and the newly received data is discarded. This process is repeated for each new sample received until at least one empty FIFO entry exists. When the RCRO bit is set, an interrupt request is made.
DAI/CODEC/SSI2 RCNE: The Right Channel Receive FIFO Not Empty Flag (RCNELCNF) is a read-only bit which is set when ever the Right Channel Receive FIFO contains one or more entries of valid data and is cleared when it no longer contains any valid data. This bit can be polled when using programmed I/O to remove remaining data from the receive FIFO. This bit does not request an interrupt.
DAI/CODEC/SSI2 1616 buffer. Data from this buffer is then serialized and sent to or received from the codec sound device. When the codec is enabled, the codec interrupt CSINT is generated repetitively at 1/8th of the byte transfer rate and the state of the FIFOs can be read in the system flags register. The net data transfer rate to/from the codec device is 8 KBps, giving an interrupt rate of 1 kHz. 16 EP7309/11/12 User’s Manual - DS508UM4 Copyright Cirrus Logic, Inc.
DAI/CODEC/SSI2 16 This page intentionally blank. 16-22 Copyright Cirrus Logic, Inc.
17UART and SIR Encoder Introduction The EP73xx provides three asynchronous interfaces: two Universal Asynchronous Receiver/Transmitter (UART) and one SIR encoder. The SIR (IrDA) encoder shares resources with one of the UARTs. This provides resources for bi-directional communication with external IrDA compliant devices as well as PCs for debugging and basic communication.
UART and SIR Encoder ; ldr str ldr ldr orr str ; 17 r1, r1, r1, r0, r0, r0, =UART1 [r12, #0x04C0] ; UART1 Configured 0x8000.04C0 =UART1EN [r12, #0x100] r0, r1 ; Set UART1EN bit [r12, #0x100] ; Store to SYSCON1 0x8000.0100 Operational Overview Both UARTs offer similar functionality to National Semiconductor’s 16C550A device and can support bit rates of up to 115.2 kbps. Each one includes two 16-byte FIFOs used for transmit and receive data. Baud rates are frequency dependent.
UART and SIR Encoder 1717 Table 17-3: UART Bit Rate in PLL Clock Mode (74 MHz) Divisor Value Bit Rate Running from the PLL Clock 0 — 1 115200 2 76800 3 57600 5 38400 11 19200 15 14400 23 9600 95 2400 191 1200 2094 110 17 Table 17-4: UART Bit Rate from 13 MHz Clock Divisor Value Bit Rate Running from 13 MHz Clock Error on 13 MHz Value 0 116071 0.75% 1 58036 0.75% 2 36890 0.75% 5 19345 0.75% 7 9673 0.75% 47 2416 0.42% 96 1196 0.28% 1054 110.02 0.
UART and SIR Encoder enabled) is half-empty. Same condition applies during transmit if the FIFOs are not enabled. An interrupt will be generated when there is no data in the UART holding register. The third interrupt is the modem interrupt UMSINT and will be active if either the two modem status lines (CTS or DTS) change state SIR Encoder UART1 shares its FIFOs with an IrDA (Infrared Data Association) SIR protocol encoder. This encoder can be enabled from SYSCON1 at SIREN (bit 15).
UART and SIR Encoder UART Data Registers (UARTDR1 and UARTDR2) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 NA Address: 10 9 8 OVERR PARER R FRMER R RX data 0x8000.0480 and 0x8000.1480, Read / Write Bit Descriptions: RX data: 8-bit data read and write for all data transfers to and from the FIFOs. Data written to these registers is pushed onto a 16-byte holding FIFO if enabled.
UART and SIR Encoder Bit Rate and Line Control Registers (UBRLCR1 and UBRLCR2) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 WRDLEN 15 14 13 12 XSTOP EVENPR T PRTEN BREAK 17 11 Address: 10 9 8 7 6 5 4 3 2 16 FIFOEN 1 0 Bit Rate Divisor 0x8000.04C0 and 0x8000.14C0, Read / Write Bit Descriptions: Bit rate divisor:This 12-bit field sets the bit rate. If the system is operating from PLL clock, then the bit rate divider is fed by a clock frequency of 3.6864 MHz.
UART and SIR Encoder 1717 Table 17-5: Word Length Selection (Continued) (Continued) WRDLEN Word Length 01 6 bits 10 7 bits 11 8 bits 17 EP7309/11/12 User’s Manual - DS508UM4 Copyright Cirrus Logic, Inc.
UART and SIR Encoder 17 This page intentionally blank. 17-8 Copyright Cirrus Logic, Inc.
ABoot Code 00000000 uart_boot_base 00000000 E3A0C102 MOV r12, #HwRegisterBase ; R12 = 0x80000000 00000004 00000004 E3A08201 MOV r8, #InternalRamBase ; R8 = 0x10000000 00000008 0000000C 0000000C 0000000C 0000000C 0000000C 0000000C 0000000C 0000000C 0000000C 0000000C E2889B02 ADD 000004C0 Hw_UBRLCR1 EQU 00000017 Hw_BR9600 EQU 0000000B Hw_BR9600_13 EQU 0x04c0 0x00000017 0x0000000b 0000000C 0000000C 0000000C 00000010 00000014 00000014 00000018 0000001C 0000001C 00000020 00000024 00000028 00060000 Hw_WRDLE
Boot Code 0000003C 00000040 00000044 00000044 00000044 00000048 0000004C 00000050 00000054 00000054 00000054 00000054 A E3110501 TST 1AFFFFFC BNE r1, #Hw_URXFE1 uart_ready_loop ;;; Read E59C0480 LDR E4C80001 STRB E1580009 CMP BAFFFFF8 BLT the data, store it, and accumulate checksum r0, [r12, #Hw_UARTDR1] ; Read data r0, [r8], #1 ; Save it in memory r8, r9 uart_ready_loop ; Do more if end of buffer not reached ;;; All received, send end flag E3A0003E MOV r0, #EndFlag 00000058 E5CC0480 STRB r0, [r12,
1Index Index B Boot Mode External 6-2 Internal 6-2 C Cache 2-5 clocks CPU 2-9 External 13 MHz 2-11 CPU clocks 2-9 State Control 2-12 Idle State 2-13 Standby State 2-12 D Debug Interface 2-7 DMA Controller 9-3 E Endianess 6-4 External Boot Mode 6-2 I Internal Boot Mode 6-2 Interrupt Latencies in Different States 4-6 Idle State 4-6 Operating State 4-6 Standby State 4-7 Listing 4-5 Operation 4-4 Priorities 4-4 Types 4-4 M Memory Map 1-2 MMU 2-4 P Pin Description 1-6 pin descriptions, external signal func
Index TLB 2-5 U UART 1-11 W Write Buffer 2-6 Index-2 Copyright Cirrus Logic, Inc.
