Owner's manual
DS508F2 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) 39
EP7312
High-Performance, Low-Power System on Chip
256-Ball PBGA Pinout (Top View)
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A VDDIO nCS[4] nCS[1] SDCLK SDQM[3] DD[1] M VDDIO D[0] D[2] A[3] VDDIO A[6] MOSCOUT VDDOSC VSSIO A
B nCS[5] VDDIO nCS[3]
nMOE/
nSDCAS
VDDIO nSDCS[1] DD[2] CL[1] VDDCORE D[1] A[2] A[4] A[5] WAKEUP VDDIO nURESET B
C VDDIO EXPCLK VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO nPOR nEXTPWR C
D
WRITE/
nSDRAS
EXPRDY VSSIO VDDIO nCS[2]
nMWE/
nSDWE
nSDCS[0] CL[2] VSSRTC D[4] nPWRFL MOSCIN VDDIO VSSIO D[7] D[8] D
E RXD[2] PB[7] TDI WORD VSSIO nCS[0] SDQM[2] FRM A[0] D[5] VSSOSC VSSIO
nMEDCHG/
nBROM
VDDIO D[9] D[10] E
F PB[5] PB[3] VSSIO TXD[2]
RUN/
CLKEN
VSSIO SDCKE DD[3] A[1] D[6] VSSRTC BATOK nBATCHG VSSIO D[11] VDDIO F
G PB[1] VDDIO TDO PB[4] PB[6] VSSCore VSSRTC DD[0] D[3] VSSRTC A[7] A[8] A[9] VSSIO D[12] D[13] G
H PA[7] PA[5] VSSIO PA[4] PA[6] PB[0] PB[2] VSSRTC VSSRTC A[10] A[11] A[12]
A[13]/
DRA[14]
VSSIO D[14] D[15] H
J PA[3] PA[1] VSSIO PA[2] PA[0] TXD[1] CTS VSSRTC VSSRTC
A[17]/
DRA[10]
A[16]/
DRA[11]
A[15]/
DRA[12]
A[14]/
DRA[13]
nTRST D[16] D[17] J
K LEDDRV PHDIN VSSIO DCD nTEST[1] EINT[3] VSSRTC ADCIN COL[4] TCLK D[20] D[19] D[18] VSSIO VDDIO VDDIO K
L RXD[1] DSR VDDIO nEINT[1]
PE[2]/
CLKSEL
VSSRTC
PD[0]/
LEDFLSH
VSSRTC COL[6] D[31] VSSRTC
A[22]/
DRA[5]
A[21]/
DRA[6]
VSSIO
A[18]/
DRA[9]
A[19]/
DRA[8]
L
M nTEST[0] nEINT[2] VDDIO
PE[0]/
BOOTSEL[0]
TMS VDDIO SSITXFR DRIVE[1] FB[0] COL[0] D[27] VSSIO
A[23]/
DRA[4]
VDDIO
A[20]/
DRA[7]
D[21] M
N nEXTFIQ
PE[1]/
BOOTSEL[1]
VSSIO VDDIO PD[5] PD[2] SSIRXDA ADCCLK SMPCLK COL[2] D[29] D[26] HALFWORD VSSIO D[22] D[23] N
P VSSRTC RTCOUT VSSIO VSSIO VDDIO VSSIO VSSIO VDDIO VSSIO VDDIO VSSIO VSSIO VDDIO VSSIO D[24] VDDIO P
R RTCIN VDDIO PD[4] PD[1] SSITXDA nADCCS VDDIO ADCOUT COL[7] COL[3] COL[1] D[30]
A[27]/
DRA[0]
A[25]/
DRA[2]
VDDIO
A[24]\
DRA[3]
R
T VDDRTC
PD[7]/
SDQM[1]
PD[6]/
SDQM[0]
PD[3] SSICLK SSIRXFR VDDCORE DRIVE[0] FB[1] COL[5] VDDIO BUZ D[28]
A[26]/
DRA[1]
D[25] VSSIO T