Owner's manual
DS508F2 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) 31
EP7312
High-Performance, Low-Power System on Chip
208-Pin LQFP Pin Diagram
Note: 1. N/C should not be grounded but left as no connects.
160
159
158
157
53
54
55
56
57
58
59
60
61
62
63
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
106
107
108
109
110
112
113
114
115
116
117
118
119
120
121
64
65
67
68
69
70
71
72
73
74
75
66
98
99
100
101
102
103
104
122
124
125
126
127
128
129
130
105
131
132
133
134
156
155
154
153
152
151
150
149
148
147
146
145
144
143
140
139
138
137
136
141
142
135
161
162
163
164
165
166
167
168
169
170
171
172
173
174
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
201
202
203
204
205
206
207
208
200
175
176
177
178
179
123
111
EP7312
208-Pin LQFP
(Top View)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
51
50
52
1
nEXTPWR
BATOK
nPOR
VSSOSC
VDDOSC
MOSCIN
MOSCOUT
nURESET
WAKEUP
A[6]
D[6]
A[5]
D[5]
VDDIO
VSSIO
A[4]
D[4]
A[3]
D[3]
nPWRFL
A[2]
D[2]
A[1]
A[0]
D[0]
VDDCORE
VSSIO
VDDIO
CL[2]
CL[1]
FRM
M
DD[2]
DD[1]
DD[0]
nSDCS[1]
SDQM[3]
SDQM[2]
VDDIO
VSSIO
SDCLK
nMWE/nSDWE
nMOE/nSDCAS
nCS[0]
nCS[1]
nCS[2]
nCS[3]
D[7]
A[7]
D[8]
A[8]
D[9]
D[10]
A[10]
VSSIO
VDDIO
A[11]
D[12]
A[12]
D[13]
A[13]\DRA[14]
D[14]
DD[3]
D[17]
D[15]
A[17]
/DRA[10]
nTRST
VSSIO
VDDIO
D[18]
A[18
/DRA[9]
D[19]
A[19]
/DRA[8]
D[20]
VSSIO
A[21]
/DRA[6]
D[22]
D[23]
A[23]
/DRA[4]
D[24]
VSSIO
VDDIO
A[24]
/DRA[3]
HALFWORD
A[14]/DRA[13]
nBATCHG
A[25]/DRA[2]
D[25]
D[27]
A[27]/DRA[0]
VSSIO
D[28]
D[29]
D[30]
D[31]
BUZ
COL[0]
COL[1]
TCLK
VDDIO
COL[2]
COL[3]
COL[4]
COL[5]
COL[6]
COL[7]
FB[0]
VSSIO
FB[1]
ADCOUT
ADCCLK
DRIVE[0]
VDDIO
PD[2]
VSSIO
VSSCORE
nADCCS
ADCIN
SSIRXDA
SSIRXFR
SSITXDA
SSITXFR
VSSIO
SSICLK
PD[0]/LEDFLSH
PD[1]
PD[3]
A[22]
/DRA[5]
PD[4]
VDDIO
PD[5]
PD[6]/SDQM[0]
DRIVE[1]
PD[7]/SDQM[1]
D[26]
A[15]
/DRA[12]
D[16]
A[16]
/DRA[11]
nCS[4]
VDDCORE
A[26]/DRA[1]
D[21]
TMS
A[20]
/DRA[7]
SMPCLK
D[11]
A[9]
D[1]
VSSCORE
nSDCS[0]
SDCKE
VSSIO
VSSIO
VSSIO
VSSIO
EXPCLK
WORD
WRITE/nSDRAS
RUN/CLKEN
EXPRDY
PB[7]
PB[6]
PB[5]
PB[4]
PB[3]
PB[2]
PB[1]
VSSIO
TDI
VDDIO
TDO
PE[2]/CLKSEL
nEXTFIQ
PA[6]
PA[5]
PA[4]
PA[3]
PA[2]
PA[1]
PA[0]
LEDDRV
TXD[2]
PHDIN
CTS
RXD[2]
DCD
DSR
RTCOUT
RTCIN
VSSIO
PA[7]
VDDIO
VSSIO
nCS[5]
PB[0]
TXD[1]
RXD[1]
nTEST[1]
nTEST[0]
EINT[3]
nEINT[2]
nEINT[1]
PE[1]BOOTSEL[1]
PE[0]BOOTSEL[0]
N/C
VSSRTC
VDDRTC
Figure 16. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram
nMEDCHG/nBROM