Owner's manual
28 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) DS508F2
EP7312
High-Performance, Low-Power System on Chip
LCD Interface
Parameter Symbol Min Max Unit
CL[2] falling to CL[1] rising delay time
t
CL1d
10 25 ns
CL[1] falling to CL[2] rising delay time
t
CL2d
80 3,475 ns
CL[1] falling to FRM transition time
t
FRMd
300 10,425 ns
CL[1] falling to M transition time
t
Md
10 20 ns
CL[2] rising to DD (display data) transition time
t
DDd
10 20 ns
CL[2]
CL[1]
FRM
M
DD [3:0]
t
CL1d
t
FRMd
t
Md
t
DDd
t
CL2d
Figure 13. LCD Controller Timing Measurement