Owner's manual

DS508F2 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) 27
EP7312
High-Performance, Low-Power System on Chip
SSI2 Interface
Parameter Symbol Min Max Unit
SSICLK period (slave mode)
t
clk_per
185 2050 ns
SSICLK high time
t
clk_high
925 1025 ns
SSICLK low time
t
clk_low
925 1025 ns
SSICLK rise/fall time
t
clkrf
318ns
SSICLK rising edge to RX and/or TX frame sync high time
t
FRd
-3ns
SSICLK rising edge to RX and/or TX frame sync low time
t
FRa
-8ns
SSIRXFR and/or SSITXFR period
t
FR_per
960 990 ns
SSIRXDA setup to SSICLK falling edge time
t
RXs
37ns
SSIRXDA hold from SSICLK falling edge time
t
RXh
37ns
SSICLK rising edge to SSITXDA data valid delay time
t
TXd
-2ns
SSITXDA valid time
t
TXv
960 990 ns
SSI
CLK
SSIRXFR/
SSITXFR
SSI
TXDA
SSI
RXDA
D1D7
D7
D2
D2 D1
D0
D0
t
clk_per
t
clk_high
t
clk_low
t
FRd
t
FR_per
t
RXs
t
TXd
t
FRa
t
RXh
t
clkrf
t
TXv
Figure 12. SSI2 Interface Timing Measurement