Owner's manual

26 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) DS508F2
EP7312
High-Performance, Low-Power System on Chip
SSI1 Interface
Parameter Symbol Min Max Unit
ADCCLK falling edge to nADCCSS deassert delay time
t
Cd
910ms
ADCIN data setup to ADCCLK rising edge time
t
INs
-15ns
ADCIN data hold from ADCCLK rising edge time
t
INh
-14ns
ADCCLK falling edge to data valid delay time
t
Ovd
 713ns
ADCCLK falling edge to data invalid delay time
t
Od
 23 ns
ADC
CLK
nADC
CSS
ADCIN
ADC
OUT
t
INs
t
INh
t
Cd
t
Od
t
Ovd
Figure 11. SSI1 Interface Timing Measurement