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DS508F2 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) 19
EP7312
High-Performance, Low-Power System on Chip
SDRAM Burst Write Cycle
Note: 1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal
SDCLK
SDCS
SDRAS
SDCAS
SDQM
ADDR
DATA
SDMWE
0
D1
ADRAS
ADCAS
D4D3D2
t
CSa
t
RAa
t
CAa
t
CSa
t
CSd
t
RAd
t
CSd
t
CAd
t
ADv
t
DAd
t
ADv
t
DAd
t
DAd
t
DAd
t
MWa
t
MWd
Figure 5. SDRAM Burst Write Cycle Timing Measurement