Owner's manual

18 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) DS508F2
EP7312
High-Performance, Low-Power System on Chip
SDRAM Burst Read Cycle
Note: 1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal.
ADRAS ADCAS
SDCLK
SDCS
SDRAS
SDCAS
SDQM
[0:3]
ADDR
DATA
SDMWE
D1 D4D3D2
t
ADv
t
ADv
t
CSd
t
CSa
t
CSa
t
CAa
t
RAd
t
CSd
t
CAd
t
RAa
t
DAh
t
DAs
t
DAh
t
DAs
t
DAh
t
DAs
t
DAh
t
DAs
t
RAnv
Figure 4. SDRAM Burst Read Cycle Timing Measurement