Owner's manual

DS508F2 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) 17
EP7312
High-Performance, Low-Power System on Chip
SDRAM Load Mode Register Cycle
Note: 1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal
SDCLK
SDCS
SDRAS
SDCAS
ADDR
DATA
SDQM
SDMWE
t
CSa
t
RAa
t
CAa
t
MWa
t
ADv
t
ADx
t
RAd
t
CSd
t
CAd
t
MWd
Figure 3. SDRAM Load Mode Register Cycle Timing Measurement