Owner's manual

16 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) DS508F2
EP7312
High-Performance, Low-Power System on Chip
SDRAM Interface
Figure 3 through Figure 6 define the timings associated with all phases of the SDRAM. The following table contains the values for
the timings of each of the SDRAM modes.
Parameter Symbol Min Typ Max Unit
SDCLK falling edge to SDCS assert delay time
t
CSa
024ns
SDCLK falling edge to SDCS deassert delay time
t
CSd
 3 2 10 ns
SDCLK falling edge to SDRAS assert delay time
t
RAa
137ns
SDCLK falling edge to SDRAS deassert delay time
t
RAd
 3 1 10 ns
SDCLK falling edge to SDRAS invalid delay time
t
RAnv
247ns
SDCLK falling edge to SDCAS assert delay time
t
CAa
 22 5 ns
SDCLK falling edge to SDCAS deassert delay time
t
CAd
 50 3 ns
SDCLK falling edge to ADDR transition time
t
ADv
 31 5 ns
SDCLK falling edge to ADDR invalid delay time
t
ADx
 22 5 ns
SDCLK falling edge to SDMWE assert delay time
t
MWa
 31 5 ns
SDCLK falling edge to SDMWE deassert delay time
t
MWd
 40 4 ns
DATA transition to SDCLK falling edge time
t
DAs
2--ns
SDCLK falling edge to DATA transition hold time
t
DAh
1--ns
SDCLK falling edge to DATA transition delay time
t
DAd
0 - 15 ns