Owner's manual
DS508F2 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) 15
EP7312
High-Performance, Low-Power System on Chip
Timings
Timing Diagram Conventions
This data sheet contains timing diagrams. The following key explains the components used in these diagrams. Any variations are
clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated.
Timing Conditions
Unless specified otherwise, the following conditions are true for all timing measurements. All characteristics are specified at
V
DDIO
= 3.1 - 3.5 V and V
SS
= 0 V over an operating temperature of -40C to +85C. Pin loadings is 50 pF. The timing values are
referenced to 1/2 V
DD
.
Clock
High to Low
High/Low to High
Bus C hange
Bus Valid
Undefined/Invalid
V a lid B u s to T ris ta te
Bus/Signal O m ission
Figure 2. Legend for Timing Diagrams