Owner's manual

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Copyright Cirrus Logic, Inc. 2011

DS508F2

http://www.cirrus.com

High-performance,

Low-power, System-on-chip

with SDRAM & Enhanced

Digital Audio Interface

EP7312 Data Sheet

OVERVIEW

BLOCK DIAGRAM

FEATURES

(cont.)

FEATURES

ARM

720T Processor

— ARM7TDMI CPU Operating at Speeds of 74 and

90 MHz

— 8 kBytes of Four-way Set-associative Cache

— MMU with 64-entry TLB

— Thumb™ Code Support Enabled

Ultra low power

— 90 mW at 74 MHz Typical

— 108 mW at 90 MHz Typical

— <.03 mW in the Standby State

Advanced Audio Decoder/decompression Capability

— Supports bit streams with adaptive bit rates.

— Allows for support of multiple audio decompression

algorithms (MP3, WMA, AAC, Audible, etc.).

LCD

Controller

Boot

ROM

MaverickKey

ARM7TDMI CPU Core

MMU

8 KB

Cache

Write

Buffer

Internal Data Bus

EPB Bus

Memory Controller

SDRAM I/FSRAM I/F

On-chip SRAM

48 KB

ICE-JTAG

Clocks &

Timers

Keypad&

Touch

Screen I/F

Interrupts,

PWM & GPIO

Bus

Bridge

(2) UARTs

w/ IrDA

Power

Management

Serial

Interface

Digital

Audio

Interface

ARM720T

SERIAL PORTS

USER INTERFACE

OVERVIEW

The Cirrus Logic

™

EP7312 is designed for ultra-low-power

portable and line-powered applications such as portable

consumer entertainment devices, home and car audio juke box

systems, and general purpose industrial control applications, or

any device that features the added capability of digital audio

compression & decompression. The core-logic functionality of

the device is built around an ARM720T processor with

8 kBytes of four-way set-associative unified cache and a write

buffer. Incorporated into the ARM720T is an enhanced

memory management unit (MMU) which allows for support of

sophisticated operating systems like Microsoft

Windows

CE and Linux

MEMORY and STORAGE

Summary of content (54 pages)

PAGE 1
EP7312 Data Sheet FEATURES High-performance, Low-power, System-on-chip with SDRAM & Enhanced Digital Audio Interface ARM®720T Processor — ARM7TDMI CPU Operating at Speeds of 74 and 90 MHz — 8 kBytes of Four-way Set-associative Cache — MMU with 64-entry TLB — Thumb™ Code Support Enabled Ultra low power — 90 mW at 74 MHz Typical — 108 mW at 90 MHz Typical — <.03 mW in the Standby State Advanced Audio Decoder/decompression Capability — Supports bit streams with adaptive bit rates.
PAGE 2
EP7312 High-Performance, Low-Power System on Chip FEATURES (cont) 48 KBytes of On-chip SRAM MaverickKey™ IDs — 32-bit unique ID can be used for DRM-compliant 128bit random ID. Available in 74 and 90 MHz clock speeds. LCD controller — Interfaces directly to a single-scan panel monochrome STN LCD. — Interfaces to a single-scan panel color STN LCD with minimal external glue logic.
PAGE 3
EP7312 High-Performance, Low-Power System on Chip Table of Contents FEATURES ...........................................................................................................................................1 OVERVIEW ...........................................................................................................................................1 FEATURES (cont) ...............................................................................................................................
PAGE 4
EP7312 High-Performance, Low-Power System on Chip SSI2 Interface ..................................................................................................................................................... 27 LCD Interface ...................................................................................................................................................... 28 JTAG Interface ..............................................................................................................
PAGE 5
EP7312 High-Performance, Low-Power System on Chip List of Figures Figure 1. A Fully-Configured EP7312-Based System ...................................................................................................12 Figure 2. Legend for Timing Diagrams .........................................................................................................................15 Figure 3. SDRAM Load Mode Register Cycle Timing Measurement .........................................................................
PAGE 6
EP7312 High-Performance, Low-Power System on Chip Description of the EP7312’s Components, Functionality, and Interfaces The following sections describe the EP7312 in more detail. Processor Core - ARM720T The EP7312 incorporates an ARM 32-bit RISC micro controller that controls a wide range of on-chip peripherals. The processor utilizes a three-stage pipeline consisting of fetch, decode and execute stages.
PAGE 7
EP7312 High-Performance, Low-Power System on Chip The second is the programmable 16- or 32-bit-wide SDRAM interface that allows direct connection of up to two banks of SDRAM, totaling 512 Mb. To assure the lowest possible power consumption, the EP7312 supports self-refresh SDRAMs, which are placed in a low-power state by the device when it enters the low-power Standby State. Table 3 shows the SDRAM Interface pin assignments. Table 3.
PAGE 8
EP7312 High-Performance, Low-Power System on Chip CODEC Interface Synchronous Serial Interface The EP7312 includes an interface to telephony-type CODECs for easy integration into voice-over-IP and other voice communications systems. The CODEC interface is multiplexed to the same pins as the DAI and SSI2. Table 6 shows the CODEC Interface Pin Assignments. The EP7312 Synchronous Serial Interface has these features: Table 6.
PAGE 9
EP7312 High-Performance, Low-Power System on Chip strobes for each keyboard column signal. The pins of Port A, when configured as inputs, can be selectively OR'ed together to provide a keyboard interrupt that is capable of waking the system from a STANDBY or IDLE state.
PAGE 10
EP7312 High-Performance, Low-Power System on Chip DC-to-DC Converter Interface (PWM) Table 16. Hardware Debug Interface Pin Assignments • Provides two 96 kHz clock outputs with programmable duty ratio (from 1-in-16 to 15-in-16) that can be used to drive a positive or negative DC to DC converter Table 14 shows the DC-to-DC Converter Interface pin assignments.
PAGE 11
EP7312 High-Performance, Low-Power System on Chip Pin Multiplexing Table 18 shows the pin multiplexing of the DAI, SSI2 and the CODEC. The selection between SSI2 and the CODEC is controlled by the state of the SERSEL bit in SYSCON2. The choice between the SSI2, CODEC, and the DAI is controlled by the DAISEL bit in SYSCON3 (see the EP7312 User’s Manual for more information). Table 18.
PAGE 12
EP7312 High-Performance, Low-Power System on Chip System Design As shown in system block diagram, simply adding desired memory and peripherals to the highly integrated EP7312 CRYSTAL MOSCIN CRYSTAL RTCIN completes a low-power system solution. All necessary interface logic is integrated on-chip.
PAGE 13
EP7312 High-Performance, Low-Power System on Chip ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings DC Core, PLL, and RTC Supply Voltage 2.9 V DC I/O Supply Voltage (Pad Ring) 3.6 V DC Pad Input Current 10 mA/pin; 100 mA cumulative Storage Temperature, No Power –40C to +125C Recommended Operating Conditions DC core, PLL, and RTC Supply Voltage 2.5 V  0.2 V DC I/O Supply Voltage (Pad Ring) 2.3 V - 3.
PAGE 14
EP7312 High-Performance, Low-Power System on Chip Symbol CI/O Parameter Transceiver capacitance IDDSTANDBY @ 25 C IDDSTANDBY @ 70 C IDDSTANDBY @ 85 C Standby current consumption1 Core, Osc, RTC @2.5 V I/O @ 3.3 V Standby current consumption1 Core, Osc, RTC @2.5 V I/O @ 3.3 V Typ Max Unit 8 - 10.0 pF - 77 41 - - - 570 111 Core, Osc, RTC @2.5 V I/O @ 3.3 V Idle current consumption1 Core, Osc, RTC @2.5 V I/O @ 3.3 V IDDIDLE at 90 MHz Idle current consumption1 Core, Osc, RTC @2.
PAGE 15
EP7312 High-Performance, Low-Power System on Chip Timings Timing Diagram Conventions This data sheet contains timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated.
PAGE 16
EP7312 High-Performance, Low-Power System on Chip SDRAM Interface Figure 3 through Figure 6 define the timings associated with all phases of the SDRAM. The following table contains the values for the timings of each of the SDRAM modes.
PAGE 17
EP7312 High-Performance, Low-Power System on Chip SDRAM Load Mode Register Cycle SDCLK tCSa tCSd tRAa tRAd tCAa tCAd SDCS SDRAS SDCAS tADv tADx ADDR DATA SDQM SDMWE tMWa tMWd Figure 3. SDRAM Load Mode Register Cycle Timing Measurement Note: DS508F2 1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
PAGE 18
EP7312 High-Performance, Low-Power System on Chip SDRAM Burst Read Cycle SDCLK tCSa SDCS tCSa tCSd tCSd tRAa SDRAS tRAnv tRAd tCAa tCAd SDCAS tADv ADDR tADv ADRAS ADCAS tDAs DATA tDAs D1 tDAh tDAs D2 tDAh tDAs D3 tDAh D4 tDAh SDQM [0:3] SDMWE Figure 4. SDRAM Burst Read Cycle Timing Measurement Note: 18 1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
PAGE 19
EP7312 High-Performance, Low-Power System on Chip SDRAM Burst Write Cycle SDCLK tCSa tCSa tCSd SDCS tCSd tRAa tRAd SDRAS tCAa tCAd SDCAS tADv tADv ADCAS ADRAS ADDR tDAd tDAd D1 DATA SDQM tDAd tDAd D2 D3 D4 0 tMWa tMWd SDMWE Figure 5. SDRAM Burst Write Cycle Timing Measurement Note: DS508F2 1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
PAGE 20
EP7312 High-Performance, Low-Power System on Chip SDRAM Refresh Cycle SDCLK tCSa tCSd tRAa tRAd SDCS SDRAS tCAd SDCAS tCAa SDATA ADDR SDQM [3:0] SDMWE Figure 6. SDRAM Refresh Cycle Timing Measurement Note: 20 1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
PAGE 21
EP7312 High-Performance, Low-Power System on Chip Static Memory Figure 7 through Figure 10 define the timings associated with all phases of the Static Memory. The following table contains the values for the timings of each of the Static Memory modes.
PAGE 22
EP7312 High-Performance, Low-Power System on Chip Static Memory Single Read Cycle EXPCLK tCSd tCSh nCS tAd A nMWE tMOEd tMOEh nMOE tHWd HALFWORD tWDd WORD tDs tDh D tEXs tEXh EXPRDY tWRd WRITE Figure 7. Static Memory Single Read Cycle Timing Measurement Note: 22 1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states.
PAGE 23
EP7312 High-Performance, Low-Power System on Chip Static Memory Single Write Cycle EXPCLK tCSd tCSh nCS tAd A tMWd tMWh nMWE nMOE tHWd HALFWORD tWDd WORD tDv D tEXs tEXh EXPRDY WRITE Figure 8. Static Memory Single Write Cycle Timing Measurement Note: DS508F2 1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states.
PAGE 24
EP7312 High-Performance, Low-Power System on Chip Static Memory Burst Read Cycle EXPCLK tCSd tCSh nCS tAd tAh tAh tAh A nMWE tMOEd tMOEh nMOE tHWd HALF WORD tWDd WORD tDs tDh tDs tDh tDs tDh tDs tDh D tEXs tEXh EXPRDY tWRd WRITE Figure 9. Static Memory Burst Read Cycle Timing Measurement Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive cycles that can be driven.
PAGE 25
EP7312 High-Performance, Low-Power System on Chip Static Memory Burst Write Cycle EXPCLK tCSd tCSh nCS tAh tAd tAh tAh A tMWd tMWd tMWd tMWh nMWE tMWd tMWh tMWh tMWh nMOE tHWd HALF WORD WORD tWDd tDv tDnv tDv tDnv tDv tDnv tDv D tEXs tEXh EXPRDY WRITE Figure 10. Static Memory Burst Write Cycle Timing Measurement Note: DS508F2 1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive cycles that can be driven.
PAGE 26
EP7312 High-Performance, Low-Power System on Chip SSI1 Interface Parameter Symbol Min Max Unit ADCCLK falling edge to nADCCSS deassert delay time tCd 9 10 ms ADCIN data setup to ADCCLK rising edge time tINs - 15 ns ADCIN data hold from ADCCLK rising edge time tINh - 14 ns ADCCLK falling edge to data valid delay time tOvd 7 13 ns ADCCLK falling edge to data invalid delay time tOd 2 3 ns ADC CLK tCd nADC CSS tINs tINh ADCIN tOvd tOd ADC OUT Figure 11.
PAGE 27
EP7312 High-Performance, Low-Power System on Chip SSI2 Interface Parameter Symbol Min Max Unit SSICLK period (slave mode) tclk_per 185 2050 ns SSICLK high time tclk_high 925 1025 ns SSICLK low time tclk_low 925 1025 ns SSICLK rise/fall time tclkrf 3 18 ns SSICLK rising edge to RX and/or TX frame sync high time tFRd - 3 ns SSICLK rising edge to RX and/or TX frame sync low time tFRa - 8 ns tFR_per 960 990 ns SSIRXDA setup to SSICLK falling edge time tRXs 3 7 ns SSI
PAGE 28
EP7312 High-Performance, Low-Power System on Chip LCD Interface Parameter Symbol Min Max Unit CL[2] falling to CL[1] rising delay time tCL1d  10 25 ns CL[1] falling to CL[2] rising delay time tCL2d 80 3,475 ns CL[1] falling to FRM transition time tFRMd 300 10,425 ns CL[1] falling to M transition time tMd  10 20 ns CL[2] rising to DD (display data) transition time tDDd  10 20 ns CL[2] tCL2d tCL1d CL[1] tFRMd FRM tMd M tDDd DD [3:0] Figure 13.
PAGE 29
EP7312 High-Performance, Low-Power System on Chip JTAG Interface Parameter Symbol Min Max Units TCK clock period tclk_per 2 - ns TCK clock high time tclk_high 1 - ns TCK clock low time tclk_low 1 - ns JTAG port setup time tJPs - 0 ns JTAG port hold time tJPh - 3 ns JTAG port clock to output tJPco - 10 ns JTAG port high impedance to valid output tJPzx - 12 ns JTAG port valid output to high impedance tJPxz - 19 ns tclk_per tclk_high tclk_low TCK tJPs tJPh TMS
PAGE 30
EP7312 High-Performance, Low-Power System on Chip Packages 208-Pin LQFP Package Characteristics 29.60 (1.165) 30.40 (1.197) 27.80 (1.094) 28.20 (1.110) 0.17 (0.007) 0.27 (0.011) 27.80 (1.094) 28.20 (1.110) EP7312 29.60 (1.165) 30.40 (1.197) 208-Pin LQFP 0.50 (0.0197) BSC Pin 1 Indicator Pin 208 Pin 1 1.35 (0.053) 1.45 (0.057) 0.45 (0.018) 0.75 (0.030) 1.00 (0.039) BSC 0 MIN 7 MAX 0.09 (0.004) 0.20 (0.008) 0.05 (0.002) 0.15 (0.006) 1.40 (0.055) 1.60 (0.063) Figure 15.
PAGE 31
EP7312 High-Performance, Low-Power System on Chip 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 nURESET nMEDCHG/nBROM nPOR BATOK nEXTPWR nBATCHG D[7] VSSIO A[7] D[8] A[8] D[9] A[9] D[10] A[10] D[11] VSSIO VDDIO A[11] D[12] A[12] D[13] A[13]\DRA[14] D[14] A[14]/DRA[13] D[15] A[15]/DRA[12] D[16] A[16]/DRA[11] D[17] A[17]/DRA[10] nTRST VSSIO VDDIO D
PAGE 32
EP7312 High-Performance, Low-Power System on Chip 208-Pin LQFP Numeric Pin Listing Table 20. 208-Pin LQFP Numeric Pin Listing 32 Pin No. Signal Reset State Type Description 1 nCS[5] Low O Chip select 5 2 3 VDDIO Pad Pwr Digital I/O power, 3.
PAGE 33
EP7312 High-Performance, Low-Power System on Chip Table 20. 208-Pin LQFP Numeric Pin Listing (Continued) Pin No.
PAGE 34
EP7312 High-Performance, Low-Power System on Chip Table 20. 208-Pin LQFP Numeric Pin Listing (Continued) Pin No.
PAGE 35
EP7312 High-Performance, Low-Power System on Chip Table 20. 208-Pin LQFP Numeric Pin Listing (Continued) DS508F2 Pin No. Signal 118 D[20] † Strength 1 Reset State Type Low I/O Data I/O System byte address / SDRAM address Description 119 A[19]/DRA[8] 1 Low O 120 D[19] 1 Low I/O Data I/O 121 A[18]/DRA[9] 1 Low O System byte address / SDRAM address 122 D[18] 1 Low I/O Data I/O 123 VDDIO Pad Pwr Digital I/O power, 3.
PAGE 36
EP7312 High-Performance, Low-Power System on Chip Table 20. 208-Pin LQFP Numeric Pin Listing (Continued) Pin No.
PAGE 37
EP7312 High-Performance, Low-Power System on Chip Table 20. 208-Pin LQFP Numeric Pin Listing (Continued) Pin No. Signal 206 nCS[2] 207 nCS[3] 208 nCS[4] Reset State Type Description 1 High O Chip select 2 1 High O Chip select 3 1 High O Chip select 4 † Strength * “With p/u” means with internal pull-up of 100 KOhms on the pin. † Strength 1 = 4 ma Strength 2 = 12 ma ‡ Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions. DS508F2 Copyright Cirrus Logic, Inc.
PAGE 38
EP7312 High-Performance, Low-Power System on Chip 256-Ball PBGA Package Characteristics 0.85 (0.034) ±0.05 (.002) 17.00 (0.669) ±0.20 (.008) Pin 1 Corner D1 0.40 (0.016) ±0.05 (.002) 15.00 (0.590) ±0.20 (.008) 30° TYP Pin 1 Indicator 17.00 (0.669) ±0.20 (.008) E1 15.00 (0.590) ±0.20 (.008) 2 Layer 0.36 (0.014) ±0.09 (0.004) TOP VIEW SIDE VIEW D 17.00 (0.669) Pin 1 Corner 1.00 (0.040) 1.00 (0.040) REF E 16 15 14 13 12 11 10 9 8 7 6 5 1.00 (0.040) REF 1 A B C D E F G H J K L M N P R T 1.
PAGE 39
EP7312 High-Performance, Low-Power System on Chip 256-Ball PBGA Pinout (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 A VDDIO nCS[4] nCS[1] SDCLK SDQM[3] DD[1] M VDDIO D[0] D[2] A[3] VDDIO A[6] B nCS[5] VDDIO nCS[3] nMOE/ nSDCAS VDDIO nSDCS[1] DD[2] CL[1] VDDCORE D[1] A[2] A[4] A[5] WAKEUP VDDIO nURESET B C VDDIO EXPCLK VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO nPOR nEXTPWR C D WRITE/ nSDRAS EXPRDY VSSIO VDDIO nCS[2]
PAGE 40
EP7312 High-Performance, Low-Power System on Chip 256-Ball PBGA Ball Listing The list is ordered by ball location. Table 21.
PAGE 41
EP7312 High-Performance, Low-Power System on Chip Table 21. 256-Ball PBGA Ball Listing (Continued) † Reset State Ball Location Name C14 VSSIO C15 nPOR C16 nEXTPWR D1 WRITE/nSDRAS 1 D2 EXPRDY 1 D3 VSSIO Pad ground I/O ground D4 VDDIO Pad power Digital I/O power, 3.
PAGE 42
EP7312 High-Performance, Low-Power System on Chip Table 21. 256-Ball PBGA Ball Listing (Continued) † Reset State Ball Location Name F13 nBATCHG I F14 VSSIO Pad ground F15 D[11] F16 VDDIO 42 Strength Type I/O Description Battery changed sense input I/O ground 1 Low 1 ‡ Input ‡ O ‡ I GPIO port B ‡ I GPIO port B Pad power Data I/O Digital I/O power, 3.
PAGE 43
EP7312 High-Performance, Low-Power System on Chip Table 21.
PAGE 44
EP7312 High-Performance, Low-Power System on Chip Table 21. 256-Ball PBGA Ball Listing (Continued) Ball Location 44 Name † Strength Reset State Type M6 VDDIO M7 SSITXFR 1 Low I/O DAI/CODEC/SSI2 frame sync M8 DRIVE[1] 2 High / Low I/O PWM drive output M9 FB[0] M10 COL[0] 1 High O Keyboard scanner column drive M11 D[27] 1 Low I/O Data I/O 1 Low M12 VSSIO M13 A[23]/DRA[4] Pad power Description I Pad ground O Pad power Digital I/O power, 3.
PAGE 45
EP7312 High-Performance, Low-Power System on Chip Table 21. 256-Ball PBGA Ball Listing (Continued) Reset State † Ball Location Name R5 SSITXDA 1 Low O DAI/CODEC/SSI2 serial data output R6 nADCCS 1 High O SSI1 ADC chip select R7 VDDIO Pad power Digital I/O power, 3.
PAGE 46
EP7312 High-Performance, Low-Power System on Chip Table 22. JTAG Boundary Scan Signal Ordering (Continued) 46 LQFP Pin No.
PAGE 47
EP7312 High-Performance, Low-Power System on Chip Table 22. JTAG Boundary Scan Signal Ordering (Continued) DS508F2 LQFP Pin No.
PAGE 48
EP7312 High-Performance, Low-Power System on Chip Table 22. JTAG Boundary Scan Signal Ordering (Continued) 48 LQFP Pin No.
PAGE 49
EP7312 High-Performance, Low-Power System on Chip Table 22. JTAG Boundary Scan Signal Ordering (Continued) LQFP Pin No.
PAGE 50
EP7312 High-Performance, Low-Power System on Chip CONVENTIONS Table 23. Acronyms and Abbreviations (Continued) Acronym/ Abbreviation This section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet. Acronyms and Abbreviations Table 23 lists abbreviations and acronyms used in this data sheet. Table 23.
PAGE 51
EP7312 High-Performance, Low-Power System on Chip General Conventions Hexadecimal numbers are presented with all letters in uppercase and a lowercase “h” appended or with a 0x at the beginning. For example, 0x14 and 03CAh are hexadecimal numbers. Binary numbers are enclosed in single quotation marks when in text (for example, ‘11’ designates a binary number). Numbers not indicated by an “h”, 0x or quotation marks are decimal.
PAGE 52
EP7312 High-Performance, Low-Power System on Chip Ordering Information Model Temperature EP7312-CBZ 0 to +70 °C EP7312-IBZ -40 to +85 °C. EP7312-CVZ EP7312-CV-90Z (90 MHz) EP7312-IVZ Package 256-pin PBGA, 17mm X 17mm 0 to +70 °C 208-pin LQFP. -40 to +85 °C.
PAGE 53
EP7312 High-Performance, Low-Power System on Chip Revision History Revision Date Changes PP5 JAN 2004 Preliminary release. Updated SDRAM timing. F1 AUG 2005 Updated ordering information. Added MSL data. F2 MAR 2011 Removed all lead-containing device ordering information. Removed 204-pin TFBGA package option. DS508F2 Copyright Cirrus Logic, Inc.
PAGE 54
EP7312 High-Performance, Low-Power System on Chip Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied).