User Manual

38 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) DS506F2
EP7311
High-Performance, Low-Power System on Chip
G11 A[7] O 274
D15 D[7] I/O 276
F13 nBATCHG I 279
C16 nEXTPWR I 280
F12 BATOK I 281
C15 nPOR I 282
E13 nMEDCHG/nBROM I 283
B16 nURESET I 284
B14 WAKEUP I 285
D11 nPWRFL I 286
A13 A[6] O 287
F10 D[6] I/O 289
B13 A[5] O 292
E10 D[5] I/O 294
B12 A[4] O 297
D10 D[4] I/O 299
A11 A[3] O 302
G9 D[3] I/O 304
B11 A[2] O 307
A10 D[2] I/O 309
F9 A[1] O 312
B10 D[1] I/O 314
E9 A[0] O 317
A9 D[0] I/O 319
D8 CL2 O 322
B8 CL1 O 324
E8 FRM O 326
A7 M O 328
F8 DD[3] I/O 330
B7 DD[2] I/O 333
A6 DD[1] I/O 336
G8 DD[0] I/O 339
B6 nSDCS[1] O 342
D7 nSDCS[0] O 344
A5 SDQM[3] I/O 346
E7 SDQM[2] I/O 349
F7 SDCKE I/O 352
A4 SDCLK I/O 355
Table U. JTAG Boundary Scan Signal Ordering (Continued)
PBGA
Ball
Signal Type Position