User Manual

36 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) DS506F2
EP7311
High-Performance, Low-Power System on Chip
N1 nEXTFIQ I 79
L5 PE[2]/CLKSEL I/O 80
N2 PE[1]/BOOTSEL1 I/O 83
M4 PE[0]/BOOTSEL0 I/O 86
T2 PD[7]/SDQM[1] I/O 89
T3 PD[6/SDQM[0]] I/O 92
N5 PD[5] I/O 95
R3 PD[4] I/O 98
T4 PD[3] I/O 101
N6 PD[2] I/O 104
R4 PD[1] I/O 107
L7 PD[0]/LEDFLSH O 110
T6 SSIRXFR I/O 122
K8 ADCIN I 125
R6 nADCCS O 126
M8 DRIVE1 I/O 128
T8 DRIVE0 I/O 131
N8 ADCCLK O 134
R8 ADCOUT O 136
N9 SMPCLK O 138
T9 FB1 I 140
M9 FB0 I 141
R9 COL7 O 142
L9 COL6 O 144
T10 COL5 O 146
K9 COL4 O 148
R10 COL3 O 150
N10 COL2 O 152
R11 COL1 O 154
M10 COL0 O 156
T12 BUZ O 158
L10 D[31] I/O 160
R12 D[30] I/O 163
N11 D[29] I/O 166
T13 D[28] I/O 169
R13 A[27]/DRA[0] Out 172
M11 D[27] I/O 174
T14 A[26]/DRA[1] O 177
Table U. JTAG Boundary Scan Signal Ordering (Continued)
PBGA
Ball
Signal Type Position