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Copyright Cirrus Logic, Inc. 2011

DS506F2

http://www.cirrus.com

High-performance,

Low-power, System-on-chip

with SDRAM & Enhanced

Digital Audio Interface

EP7311 Data Sheet

OVERVIEW

BLOCK DIAGRAM

FEATURES

(cont.)

ARM720T Processor

— ARM7TDMI CPU

— 8 KB of four-way set-associative cache

— MMU with 64-entry TLB

— Thumb code support enabled

Ultra low power

— 90 mW at 74 MHz typical

— 30 mW at 18 MHz typical

— 10 mW in the Idle State

— <1 mW in the Standby State

48 KB of on-chip SRAM

MaverickKey

™

IDs

— 32-bit unique ID can be used for SDMI compliance

— 128-bit random ID

Dynamically programmable clock speeds of

18, 36, 49, and 74 MHz

LCD

Controller

Boot

ROM

MaverickKey

ARM7TDMI CPU Core

MMU

8 KB

Cache

Write

Buffer

Internal Data Bus

EPB Bus

Memory Controller

SDRAM I/FSRAM I/F

On-chip SRAM

48 KB

ICE-JTAG

Clocks &

Timers

Keypad&

Touch

Screen I/F

Interrupts,

PWM & GPIO

Bus

Bridge

(2) UARTs

w/ IrDA

Power

Management

Serial

Interface

Multimedia

Codec Port

ARM720T

MEMORY AND STORAGE

USER INTERFACE

SERIAL PORTS

The Maverick™ EP7311 is designed for ultra-low-power

applications such as PDAs, smart cellular phones, and

industrial hand held information appliances. The core-logic

functionality of the device is built around an ARM720T

processor with 8 KB of four-way set-associative unified cache

and a write buffer. Incorporated into the ARM720T is an

enhanced memory management unit (MMU) which allows for

support of sophisticated operating systems like Linux

Summary of content (42 pages)

PAGE 1
EP7311 Data Sheet FEATURES High-performance, Low-power, System-on-chip with SDRAM & Enhanced Digital Audio Interface ARM720T Processor — ARM7TDMI CPU — 8 KB of four-way set-associative cache — MMU with 64-entry TLB — Thumb code support enabled Ultra low power — 90 mW at 74 MHz typical — 30 mW at 18 MHz typical — 10 mW in the Idle State — <1 mW in the Standby State 48 KB of on-chip SRAM MaverickKey™ IDs OVERVIEW The Maverick™ EP7311 is designed for ultra-low-power applications such as PDAs, smart cellular
PAGE 2
EP7311 High-Performance, Low-Power System on Chip FEATURES (cont) LCD controller — Interfaces directly to a single-scan panel monochrome STN LCD — Interfaces to a single-scan panel color STN LCD with minimal external glue logic Full JTAG boundary scan and Embedded ICE support Integrated Peripheral Interfaces — 32-bit SDRAM Interface up to 2 external banks — 8/32/16-bit SRAM/FLASH/ROM Interface — Multimedia Codec Port — Two Synchronous Serial Interfaces (SSI1, SSI2) — CODEC Sound Interface — 8×8 Keypad Sca
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EP7311 High-Performance, Low-Power System on Chip Table of Contents FEATURES .........................................................................................................................................................2 OVERVIEW ..................................................................................................................................................................2 Processor Core - ARM720T .................................................................................
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EP7311 High-Performance, Low-Power System on Chip CONVENTIONS ................................................................................................................................. 40 Acronyms and Abbreviations .............................................................................................................................. 40 Units of Measurement .........................................................................................................................................
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EP7311 High-Performance, Low-Power System on Chip List of Figures Figure 1. A Maximum EP7311 Based System ..............................................................................................................12 Figure 2. Legend for Timing Diagrams .........................................................................................................................15 Figure 3. SDRAM Load Mode Register Cycle Timing Measurement .......................................................................
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EP7311 High-Performance, Low-Power System on Chip Processor Core - ARM720T The EP7311 incorporates an ARM 32-bit RISC microcontroller that controls a wide range of on-chip peripherals. The processor utilizes a three-stage pipeline consisting of fetch, decode and execute stages. Key features include: • • • • ARM (32-bit) and Thumb (16-bit compressed) instruction sets Enhanced MMU for Microsoft Windows CE and other operating systems 8 KB of 4-way set-associative cache.
PAGE 7
EP7311 High-Performance, Low-Power System on Chip The second is the programmable 16- or 32-bit-wide SDRAM interface that allows direct connection of up to two banks of SDRAM, totaling 512 Mb. To assure the lowest possible power consumption, the EP7311 supports self-refresh SDRAMs, which are placed in a low-power state by the device when it enters the low-power Standby State. Pin Mnemonic I/O Pin Description UART 1 to enable these signals to drive an infrared communication interface directly.
PAGE 8
EP7311 High-Performance, Low-Power System on Chip CODEC Interface Synchronous Serial Interface The EP7311 includes an interface to telephony-type CODECs for easy integration into voice-over-IP and other voice communications systems. The CODEC interface is multiplexed to the same pins as the MCP and SSI2.
PAGE 9
EP7311 High-Performance, Low-Power System on Chip 64-Keypad Interface . Pin Mnemonic Matrix keyboards and keypads can be easily read by the EP7311. A dedicated 8-bit column driver output generates strobes for each keyboard column signal. The pins of Port A, when configured as inputs, can be selectively OR'ed together to provide a keyboard interrupt that is capable of waking the system from a STANDBY or IDLE state.
PAGE 10
EP7311 High-Performance, Low-Power System on Chip DC-to-DC converter interface (PWM) Hardware debug Interface • • Provides two 96 kHz clock outputs with programmable duty ratio (from 1-in-16 to 15-in-16) that can be used to drive a positive or negative DC to DC converter Full JTAG boundary scan and Embedded ICE support Pin Mnemonic Pin Mnemonic DRIVE[1:0] I/O I/O FB[1:0] I Pin Description PWM drive output PWM feedback input Table N.
PAGE 11
EP7311 High-Performance, Low-Power System on Chip Pin Multiplexing The following table shows the pin multiplexing of the MCP, SSI2 and the CODEC. The selection between SSI2 and the CODEC is controlled by the state of the SERSEL bit in SYSCON2. The choice between the SSI2, CODEC, and the MCP is controlled by the MCPSEL bit in SYSCON3 (see the EP73xx User’s Manual for more information).
PAGE 12
EP7311 High-Performance, Low-Power System on Chip System Design As shown in system block diagram, simply adding desired memory and peripherals to the highly integrated EP7311 completes a low-power system solution. All necessary interface logic is integrated on-chip.
PAGE 13
EP7311 High-Performance, Low-Power System on Chip ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings DC Core, PLL, and RTC Supply Voltage 2.9 V DC I/O Supply Voltage (Pad Ring) 3.6 V DC Pad Input Current 10 mA/pin; 100 mA cumulative Storage Temperature, No Power –40C to +125C Recommended Operating Conditions DC core, PLL, and RTC Supply Voltage 2.5 V  0.2 V DC I/O Supply Voltage (Pad Ring) 2.3 V - 3.
PAGE 14
EP7311 High-Performance, Low-Power System on Chip Symbol CI/O Parameter Transceiver capacitance IDDSTANDBY @ 25 C IDDSTANDBY @ 70 C IDDSTANDBY @ 85 C IDDidle at 74 MHz Standby current consumption1 Core, Osc, RTC @2.5 V I/O @ 3.3 V Standby current consumption1 Core, Osc, RTC @2.5 V I/O @ 3.3 V Typ Max Unit 8 - 10.0 pF - 77 41 - - - 570 111 Core, Osc, RTC @2.5 V I/O @ 3.3 V Idle current consumption1 Core, Osc, RTC @2.5 V I/O @ 3.
PAGE 15
EP7311 High-Performance, Low-Power System on Chip Timings Timing Diagram Conventions This data sheet contains timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated.
PAGE 16
EP7311 High-Performance, Low-Power System on Chip SDRAM Interface Figure 3 through Figure 6 define the timings associated with all phases of the SDRAM. The following table contains the values for the timings of each of the SDRAM modes.
PAGE 17
EP7311 High-Performance, Low-Power System on Chip SDRAM Load Mode Register Cycle SDCLK tCSa tCSd tRAa tRAd tCAa tCAd SDCS SDRAS SDCAS tADv tADx ADDR DATA SDQM tMWa tMWd SDMWE Figure 3. SDRAM Load Mode Register Cycle Timing Measurement Note: DS506F2 1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
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EP7311 High-Performance, Low-Power System on Chip SDRAM Burst Read Cycle SDCLK tCSa SDCS tCSa tCSd tCSd tRAa SDRAS tRAnv tRAd tCAa tCAd SDCAS tADv ADDR tADv ADRAS ADCAS tDAs DATA tDAs D1 tDAh tDAs D2 tDAh tDAs D3 tDAh D4 tDAh SDQM [0:3] SDMWE Figure 4. SDRAM Burst Read Cycle Timing Measurement Note: 18 1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
PAGE 19
EP7311 High-Performance, Low-Power System on Chip SDRAM Burst Write Cycle SDCLK tCSa tCSa tCSd SDCS tCSd tRAa tRAd SDRAS tCAa tCAd SDCAS tADv tADv tDAd tDAd tDAd D1 DATA SDQM ADCAS ADRAS ADDR D2 tDAd D3 D4 0 tMWa tMWd SDMWE Figure 5. SDRAM Burst Write Cycle Timing Measurement Note: DS506F2 1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
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EP7311 High-Performance, Low-Power System on Chip SDRAM Refresh Cycle SDCLK tCSa tCSd tRAa tRAd SDCS SDRAS tCAd SDCAS tCAa SDATA ADDR SDQM [3:0] SDMWE Figure 6. SDRAM Refresh Cycle Timing Measurement Note: 20 1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
PAGE 21
EP7311 High-Performance, Low-Power System on Chip Static Memory Figure 7 through Figure 10 define the timings associated with all phases of the Static Memory. The following table contains the values for the timings of each of the Static Memory modes.
PAGE 22
EP7311 High-Performance, Low-Power System on Chip Static Memory Single Read Cycle EXPCLK tCSd tCSh nCS tAd A nMWE tMOEd tMOEh nMOE tHWd HALFWORD tWDd WORD tDs tDh D tEXs tEXh EXPRDY tWRd WRITE Figure 7. Static Memory Single Read Cycle Timing Measurement Note: 22 1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states.
PAGE 23
EP7311 High-Performance, Low-Power System on Chip Static Memory Single Write Cycle EXPCLK tCSd tCSh nCS tAd A tMWd tMWh nMWE nMOE tHWd HALFWORD tWDd WORD tDv D tEXs tEXh EXPRDY WRITE Figure 8. Static Memory Single Write Cycle Timing Measurement Note: DS506F2 1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states.
PAGE 24
EP7311 High-Performance, Low-Power System on Chip Static Memory Burst Read Cycle EXPCLK tCSd tCSh nCS tAd tAh tAh tAh A nMWE tMOEd tMOEh nMOE tHWd HALF WORD tWDd WORD tDs tDh tDs tDh tDs tDh tDs tDh D tEXs tEXh EXPRDY tWRd WRITE Figure 9. Static Memory Burst Read Cycle Timing Measurement Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive cycles that can be driven.
PAGE 25
EP7311 High-Performance, Low-Power System on Chip Static Memory Burst Write Cycle EXPCLK tCSd tCSh nCS tAh tAd tAh tAh A tMWd tMWd tMWd tMWh nMWE tMWd tMWh tMWh tMWh nMOE tHWd HALF WORD WORD tWDd tDv tDnv tDv tDnv tDv tDnv tDv D tEXs tEXh EXPRDY WRITE Figure 10. Static Memory Burst Write Cycle Timing Measurement Note: DS506F2 1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive cycles that can be driven.
PAGE 26
EP7311 High-Performance, Low-Power System on Chip SSI1 Interface Parameter Symbol Min Max Unit ADCCLK falling edge to nADCCSS deassert delay time tCd 9 10 ms ADCIN data setup to ADCCLK rising edge time tINs - 15 ns ADCIN data hold from ADCCLK rising edge time tINh - 14 ns ADCCLK falling edge to data valid delay time tOvd 7 13 ns ADCCLK falling edge to data invalid delay time tOd 2 3 ns ADC CLK tCd nADC CSS tINs tINh ADCIN tOvd tOd ADC OUT Figure 11.
PAGE 27
EP7311 High-Performance, Low-Power System on Chip SSI2 Interface Parameter Symbol Min Max Unit SSICLK period (slave mode) tclk_per 185 2050 ns SSICLK high time tclk_high 925 1025 ns SSICLK low time tclk_low 925 1025 ns SSICLK rise/fall time tclkrf 3 18 ns SSICLK rising edge to RX and/or TX frame sync high time tFRd - 3 ns SSICLK rising edge to RX and/or TX frame sync low time tFRa - 8 ns tFR_per 960 990 ns SSIRXDA setup to SSICLK falling edge time tRXs 3 7 ns SSI
PAGE 28
EP7311 High-Performance, Low-Power System on Chip LCD Interface Parameter Symbol Min Max Unit CL[2] falling to CL[1] rising delay time tCL1d  10 25 ns CL[1] falling to CL[2] rising delay time tCL2d 80 3,475 ns CL[1] falling to FRM transition time tFRMd 300 10,425 ns CL[1] falling to M transition time tMd  10 20 ns CL[2] rising to DD (display data) transition time tDDd  10 20 ns CL[2] tCL2d tCL1d CL[1] tFRMd FRM tMd M tDDd DD [3:0] Figure 13.
PAGE 29
EP7311 High-Performance, Low-Power System on Chip JTAG Interface Parameter Symbol Min Max Units TCK clock period tclk_per 2 - ns TCK clock high time tclk_high 1 - ns TCK clock low time tclk_low 1 - ns JTAG port setup time tJPs - 0 ns JTAG port hold time tJPh - 3 ns JTAG port clock to output tJPco - 10 ns JTAG port high impedance to valid output tJPzx - 12 ns JTAG port valid output to high impedance tJPxz - 19 ns tclk_per tclk_high tclk_low TCK tJPs tJPh TMS
PAGE 30
EP7311 High-Performance, Low-Power System on Chip Packages 256-Ball PBGA Package Characteristics 256-Ball PBGA Package Specifications 0.85 (0.034) ±0.05 (.002) 17.00 (0.669) ±0.20 (.008) Pin 1 Corner D1 0.40 (0.016) ±0.05 (.002) 15.00 (0.590) ±0.20 (.008) 30° TYP Pin 1 Indicator 17.00 (0.669) ±0.20 (.008) E1 15.00 (0.590) ±0.20 (.008) 2 Layer 0.36 (0.014) ±0.09 (0.004) TOP VIEW SIDE VIEW D 17.00 (0.669) Pin 1 Corner 1.00 (0.040) 1.00 (0.040) REF E 16 15 14 13 12 11 10 9 8 7 6 5 1.00 (0.
PAGE 31
EP7311 High-Performance, Low-Power System on Chip 256-Ball PBGA Pinout (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 A VDDIO nCS[4] nCS[1] SDCLK SDQM[3] DD[1] M VDDIO D[0] D[2] A[3] VDDIO A[6] B nCS[5] VDDIO nCS[3] nMOE/ nSDCAS VDDIO nSDCS[1] DD[2] CL[1] VDDCORE D[1] A[2] A[4] A[5] WAKEUP VDDIO nURESET B C VDDIO EXPCLK VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO nPOR nEXTPWR C D WRITE/ nSDRAS EXPRDY VSSIO VDDIO nCS[2]
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EP7311 High-Performance, Low-Power System on Chip 256-Ball PBGA Ball Listing The list is ordered by ball location. Table T. 256-Ball PBGA Ball Listing (Continued) Table T. 256-Ball PBGA Ball Listing Ball Location Name Type A1 VDDIO Pad power nCS[4] O Chip select out A3 nCS[1] O Chip select out A4 SDCLK O SDRAM clock out A6 DD[1] O Type Description C12 VDDIO Pad power C13 VSSIO Pad ground I/O ground C14 VSSIO Pad ground I/O ground Digital I/O power, 3.
PAGE 33
EP7311 High-Performance, Low-Power System on Chip Table T. 256-Ball PBGA Ball Listing (Continued) Type Table T.
PAGE 34
EP7311 High-Performance, Low-Power System on Chip Table T. 256-Ball PBGA Ball Listing (Continued) Ball Location Name M7 SSITXFR I/O MCP/CODEC/SSI2 frame sync M8 DRIVE[1] I/O PWM drive output 34 Type Table T. 256-Ball PBGA Ball Listing (Continued) Description Ball Location Name Type Description R7 VDDIO Pad power R8 ADCOUT O SSI1 ADC serial data output Digital I/O power, 3.
PAGE 35
EP7311 High-Performance, Low-Power System on Chip JTAG Boundary Scan Signal Ordering Table U.
PAGE 36
EP7311 High-Performance, Low-Power System on Chip Table U.
PAGE 37
EP7311 High-Performance, Low-Power System on Chip Table U.
PAGE 38
EP7311 High-Performance, Low-Power System on Chip Table U.
PAGE 39
EP7311 High-Performance, Low-Power System on Chip Table U. JTAG Boundary Scan Signal Ordering (Continued) PBGA Ball Signal Type Position D6 nMWE/nSDWE O 358 B4 nMOE/nSDCAS O 360 E6 nCS[0] O 362 A3 nCS[1] O 364 D5 nCS[2] O 366 B3 nCS[3] O 368 A2 nCS[4] O 370 1) See EP7311 Users’ Manual for pin naming / functionality. 2) For each pad, the JTAG connection ordering is input, output, then enable as applicable. DS506F2 Copyright Cirrus Logic, Inc.
PAGE 40
EP7311 High-Performance, Low-Power System on Chip CONVENTIONS Table V. Acronyms and Abbreviations (Continued) Acronym/ Abbreviation This section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet. Acronyms and Abbreviations Table V lists abbreviations and acronyms used in this data sheet. Table V.
PAGE 41
EP7311 High-Performance, Low-Power System on Chip General Conventions Pin Description Conventions Hexadecimal numbers are presented with all letters in uppercase and a lowercase “h” appended or with a 0x at the beginning. For example, 0x14 and 03CAh are hexadecimal numbers. Binary numbers are enclosed in single quotation marks when in text (for example, ‘11’ designates a binary number). Numbers not indicated by an “h”, 0x or quotation marks are decimal.
PAGE 42
EP7311 High-Performance, Low-Power System on Chip Ordering Information Model Temperature EP7311M-IBZ Package -40 to +85 °C. 256-pin PBGA, 17mm X 17mm Environmental, Manufacturing, & Handling Information Model Number Peak Reflow Temp MSL Rating* Max Floor Life EP7311M-IBZ 260 °C 3 7 Days * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. Revision History Revision Date Changes PP1 NOV 2003 First preliminary release. F1 AUG 2005 Updated SDRAM timing. Added MSL data.