Instruction Manual

DS271F5 65
CS8900A
Crystal LAN™ Ethernet Controller
CIRRUS LOGIC PRODUCT DATASHEET
4.4.19 Register 16: Self Status
(SelfST, Read-only, Address: PacketPage base + 0136h)
SelfST reports the status of the EEPROM interface and the initialization process.
010110 These bits provide an internal address used by the CS8900A to identify this as the Chip Self
Status Register. When reading this register, these bits will be 010110, where the LSB corre-
sponds to Bit 0.
3,3VActive If the CS8900A is operating on a 3.3V supply, this bit is set. If the CS8900A is operating on a
5V supply, this bit is clear.
INITD If set, the CS8900A initialization, including read-in of the EEPROM, is complete.
SIBUSY If set, the EECS output pin is high indicating that the EEPROM is currently being read or pro-
grammed. The host must not write to PacketPage base + 0040h nor 0042h until SIBUSY is
clear.
EEPROMpresent If the EEDataIn pin is low after reset, there is no EEPROM present, and the EEPROMpresent
bit is clear. If the EEDataIn pin is high after reset, the CS8900A "assumes" that an EEPROM
is present, and this bit is set.
EEPROMOK If set, the checksum of the EEPROM readout was OK.
ELpresent If set, external logic for Latchable Address bus decode is present.
EEsize This bit shows the size of the attached EEPROM and is valid only if the EEPROMpresent bit
(Bit 9) and EEPROMOK bit (Bit A) are both set. If clear, the EEPROM size is either 128 words
('C56 or 'CS56) or 256 words (C66 or 'CS66). If set, the EEPROM size is 64 words ('C46 or
'CS46).
Reset value is: 0000 0000 0001 0110
4.4.20 Register 17: Bus Control
(BusCTL, Read/Write, Address: PacketPage base + 0116h)
BusCTL controls the operation of the ISA-bus interface.
010111 These bits provide an internal address used by the CS8900A to identify this as the Bus Control
Register.
76543210
INITD 3.3V Active 010110
FEDCBA9 8
EEsize ELPresent EEPROM OK
EEPROM
present
SIBUSY
76543210
Reset RxDMA 010111
FEDCBA9 8
EnableIRQ RxDMA size IOCH RDYE DMABurst MemoryE UseSA DMAextend