Owner's manual

DS692F2 51
CS8422
11.5 GPO Control 1 (05h)
GPOxSEL[3:0] – GPO Source select for GPO0 and GPO1 pins. See Table 7 for available outputs for
GPO[3:0].
11.6 GPO Control 2 (06h)
GPOxSEL[3:0] – GPO Source select for GPO2 and GPO3 pins. See Table 7 for available outputs for
GPO[3:0].
11.7 Serial Audio Input Clock Control (07h)
SAI_CLK[3:0] – Selects the serial audio input master clock-to-ILRCK ratio when the serial audio input port
is set to master mode (SIMS = 1 as shown in “Serial Audio Input Data Format (0Bh)” on page 54). Note: if
a serial audio output is sourced directly by the serial audio input port, SAI_CLK[3:0] determine the
MCLK/LRCK ratio for both serial ports if they are set to master mode.
7 6 543210
GPO0SEL3 GPO0SEL2 GPO0SEL1 GPO0SEL0 GPO1SEL3 GPO1SEL2 GPO1SEL1 GPO1SEL0
0 0 000000
7 6 543210
GPO2SEL3 GPO2SEL2 GPO2SEL1 GPO2SEL0 GPO3SEL3 GPO3SEL2 GPO3SEL1 GPO3SEL0
0 0 000000
Function Code Definition
GND 0000 Fixed low level
VL 0001 Fixed VL level.
EMPH
0010 State of EMPH bit in the incoming data stream
INT 0011 CS8422 interrupt output
C 0100 Channel status bit
U 0101 User data bit
RERR 0110 Receiver Error. Use of RERR and NVERR are described in Section 6.6.1.
NVERR 0111 Non-Validity Receiver Error (same signal as RERR except it does not become
active when validity bit error occurs). Use of RERR and NVERR are described
in Section 6.6.1.
RCBL 1000 Receiver Channel Status Block
96KHZ 1001 Defined in “PLL Status (15h)” on page 61.
192KHZ 1010 Defined in “PLL Status (15h)” on page 61.
AUDIO
1011 Non-audio indicator for decoded input stream
VLRCK 1100 Virtual LRCK, can be used to frame the C and U output data.
TX 1101 Pass through of AES/SPDIF input selected by TXSEL[2:0] in Section 11.3
“Receiver Input Control (03h)” on page 49.
SRC_UNLOCK 1110 SRC unlock indicator
XTI_OUT 1111 Buffered XTI-XTO output
Table 7. GPO Pin Configurations
76543210
SAI_CLK3 SAI_CLK2 SAI_CLK1 SAI_CLK0 SAI_MCLK Reserved Reserved Reserved
01000———