CS8422 24-bit, 192-kHz, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver Sample Rate Converter Features Digital Audio Interface Receiver Features 140 dB Dynamic Range Complete EIAJ CP1201, IEC-60958, AES3, -120 dB THD+N No External Master Clock Required Supports Sample Rates up to 211 kHz Input/Output Sample Rate Ratios from 6:1 to 1:6 Master Mode Master Clock/Sample Rate Ratio Support: 64, 96, 128, 192, 256, 384, 512, 768, 1024
CS8422 System Features SPI™ or I²C™ Software Mode and Stand-Alone Hardware Mode Flexible 3-wire Digital Serial Audio Input Port Dual Serial Audio Output Ports with Independently Selectable Data Paths Master or Slave Mode Operation for all Serial Audio Ports Time Division Multiplexing (TDM) Mode Integrated Oscillator for use with External Crystal Four General-purpose Output Pins (GPO) +3.3 V Analog Supply (VA) +1.8 V to 5.
CS8422 TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 9 1.1 Software Mode ................................................................................................................................. 9 1.2 Hardware Mode ............................................................................................................................. 11 2. CHARACTERISTICS AND SPECIFICATIONS .
CS8422 6.10.2 Software Mode Control ........................................................................................................ 35 7. SAMPLE RATE CONVERTER (SRC) .................................................................................................. 37 7.1 SRC Data Resolution and Dither ................................................................................................... 37 7.1.1 Hardware Mode Control .....................................................................
CS8422 12.4.3 Serial Copy Management System (SCMS) ......................................................................... 69 12.5 Jitter Attenuation .......................................................................................................................... 69 12.6 Jitter Tolerance ............................................................................................................................ 70 12.7 Group Delay ...................................................................
CS8422 Figure 40.Wideband FFT – 0 dBFS 1 kHz Tone, 44.1 kHz:48 kHz ...................................................................................................... 71 Figure 41.Wideband FFT – 0 dBFS 1 kHz Tone, 48 kHz:44.1 kHz ...................................................................................................... 71 Figure 42.Wideband FFT – 0 dBFS 1 kHz Tone, 48 kHz:96 kHz .........................................................................................................
CS8422 Figure 67.Dynamic Range vs. Output Sample Rate – -60 dBFS 1 kHz Tone, Fsi = 32 kHz ......................................................................................................... 75 Figure 68.Dynamic Range vs. Output Sample Rate – -60 dBFS 1 kHz Tone, Fsi = 96 kHz ......................................................................................................... 76 Figure 69.Dynamic Range vs. Output Sample Rate – -60 dBFS 1 kHz Tone, Fsi = 44.1 kHz ....................................
CS8422 LIST OF TABLES Table 1. VLRCK Behavior ......................................................................................................................... 35 Table 2. PLL Clock Ratios ......................................................................................................................... 38 Table 3. Hardware Mode Control Settings ................................................................................................ 41 Table 4.
CS8422 1. PIN DESCRIPTION Pin Name Pin # RST RMCK GPO3 OLRCK1 OSCLK1 SDOUT1 TDM_IN OLRCK2 Software Mode 32 31 30 29 28 27 26 25 RX0/RXP0 1 24 OSCLK2 RX1/RXN0 2 23 SDOUT2 VA 3 22 VL AGND 4 21 DGND Thermal Pad RX2/RXP1 5 20 VD_FILT RX3/RXN1 6 19 V_REG AD0/CS 7 18 GPO2 AD1/CDIN 8 17 GPO1 9 10 11 12 13 14 15 16 SDA/CDOUT XTI XTO ILRCK ISCLK SDIN GPO0 Top-Down View 32-Pin QFN Package SCL/CCLK 1.
CS8422 Pin Name Pin # Pin Description XTI 11 Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “SRC Master Clock” on page 38 for more details. XTO 12 Crystal Out (Output) - Crystal output for Master clock. See “SRC Master Clock” on page 38 for more details. ILRCK 13 Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN pin.
CS8422 Pin Name Pin # RST RMCK SRC_UNLOCK OLRCK1 OSCLK1 SDOUT1 TDM_IN OLRCK2 Hardware Mode 32 31 30 29 28 27 26 25 RXP0 1 24 OSCLK2 RXN0 2 23 SDOUT2 VA 3 22 VL AGND 4 21 DGND Thermal Pad RXP1 5 20 VD_FILT RXN1 6 19 V_REG SAOF 7 18 TX/U MS_SEL 8 17 C 9 10 11 12 13 14 15 16 V/AUDIO XTI XTO MCLK_OUT TX_SEL RX_SEL RCBL Top-Down View 32-Pin QFN Package NV/RERR 1.
CS8422 Pin Name Pin # Pin Description MCLK_OUT 13 Buffered MCLK (Output) - Buffered output of XTI clock. If a 20 k pull-up resistor to VL is present on this pin, the SRC MCLK source will be the PLL clock, otherwise it will be the ring oscillator. TX_SEL 14 TX Pin MUX Selection (Input) - Used to select the AES3-compatible receiver input for pass-through to the TX pin. RX_SEL 15 Receiver MUX Selection (Input) - Used to select the active AES3-compatible receiver input.
CS8422 2. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25° C.) RECOMMENDED OPERATING CONDITIONS GND = 0 V, all voltages with respect to 0 V. Parameter Power Supply Voltage Ambient Operating Temperature: Commercial Grade Symbol Min Nominal Max Units VL VA V_REG 1.71 3.135 3.135 3.
CS8422 PERFORMANCE SPECIFICATIONS - SAMPLE RATE CONVERTER XTI-XTO = 24.576 MHz; Input signal = 1.000 kHz, Measurement Bandwidth = 20 to Fso/2 Hz, and Word Width = 24-Bits. (Note 2) Parameter Min Resolution 16 Sample Rate Slave XTI/2048 Master XTI/512 Typ Max Units - 24 bits - XTI/128 XTI/128 kHz kHz Sample Rate Ratio - Upsampling - - 1:6 Fsi:Fso Sample Rate Ratio - Downsampling - - 6:1 Fsi:Fso Interchannel Gain Mismatch - 0.0 - dB Interchannel Phase Deviation - 0.
CS8422 DC ELECTRICAL CHARACTERISTICS AGND = DGND = 0 V; all voltages with respect to 0 V. Parameter Min Typ Max Units VA V_REG VL = 1.8 V VL = 2.5 V VL = 3.3 V VL = 5.0 V - 4.7 1 0.3 7.1 16.9 102.6 - µA µA µA µA µA µA Supply Current at 48 kHz Fsi and Fso VA V_REG VL = 1.8 V VL = 2.5 V VL = 3.3 V VL = 5.0 V - 18.8 15.2 2.7 3.8 5.2 5.3 - mA mA mA mA mA mA Supply Current at 192 kHz Fsi and Fso VA V_REG VL = 1.8 V VL = 2.5 V VL = 3.3 V VL = 5.0 V - 18.9 32.4 6.2 8.
CS8422 DIGITAL INTERFACE SPECIFICATIONS AGND = DGND = 0 V; all voltages with respect to 0 V.
CS8422 SWITCHING SPECIFICATIONS Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF. Parameter Min Typ Max Units RST pin Low Pulse Width (Note 7) 1 - - ms PLL Clock Recovery Sample Rate Range (Note 8) 28 - 216 kHz - 200 475 - ps RMS ps RMS 12 - 27.000 MHz 1.024 - 49.152 MHz 9 - - ns RMCK/MCLK_OUT Output Frequency - - 49.152 MHz RMCK/MCLK_OUT Output Duty Cycle 45 50 55 % - - 49.
CS8422 Parameter Symbol Min Typ Max Units tfsm - - 4.2 ns RMCK/MCLK_OUT Output Frequency (VL = 1.8 V) - - 13.5 MHz RMCK/MCLK_OUT Output Frequency (VL = 2.5 V) - - 31 MHz RMCK/MCLK_OUT Output Duty Cycle (VL = 1.8 V) 37 50 63 % RMCK/MCLK_OUT Output Duty Cycle (VL = 2.5 V) 45 50 55 % - - 49.152 MHz TDM Mode OSCLK Falling Edge to OLRCK Edge VL = 1.8 V, 2.5 V Slave Mode ISCLK Frequency ISCLK High Time tsckh 9.2 - - ns ISCLK Low Time tsckl 9.2 - - ns - - 15.
CS8422 9. Typical base band jitter in accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error (TIE) taken with 3rd order 100 Hz to 40 kHz band-pass filter. Measured with Sample Rate = 48 kHz. 10. OLRCK must remain high for at least 1 OSCLK period and at most 255 OSCLK periods in TDM Mode. 11. In TDM formatted master mode, the TDM_IN pin is not supported. 12. In TDM formatted master mode, the OSCLK frequency is fixed at 256*OLRCK.
CS8422 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF. Parameter Symbol Min Max Unit CCLK Clock Frequency fsck 0 6.0 MHz RST Rising Edge to CS Falling tsrs 500 - µs CCLK Edge to CS Falling (Note 13) tspi 500 - ns CS High Time Between Transmissions tcsh 1.
CS8422 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF. Parameter Symbol Min Max Unit SCL Clock Frequency fscl - 100 kHz RST Rising Edge to Start tirs 500 - µs Bus Free Time Between Transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low time tlow 4.7 - µs Clock High Time thigh 4.0 - µs Setup Time for Repeated Start Condition tsust 4.
CS8422 3. TYPICAL CONNECTION DIAGRAMS 3.1 Software Mode +3.3V 10 µF+ 0.1 µF +3.3V +1.8V to +5V 0.1 µF 0.1 µF 19 22 V_ R VA EG 3 VL 10 µF+ VD_FILT 20 0.1 µF 1 RX0/RXP0 AES3/SPDIF/IEC60958 Receiver Circuitry See section 12.3 for details.
CS8422 3.2 Hardware Mode +3.3V 10 µF + 0.1 µF +3.3V +1.8V to +5V + 0.1 µF 0.1 µF 3 19 V_ R VA EG 22 VL 10 µF 1 RXP0 VD_FILT 20 0.1 µF 2 RXN0 AES3/SPDIF/IEC60958 Receiver Circuitry See section 12.3 for details.
CS8422 4. OVERVIEW The CS8422 is a 24-bit, high performance, monolithic CMOS stereo asynchronous sample rate converter with integrated digital audio interface receiver that decodes audio data according to EIAJ CP1201, IEC-60958, AES3, and S/PDIF interface standards. Audio data is input through either a 3-wire serial audio port or the AES3-compatible digital interface receiver. Audio data is output through one of two 3-wire serial audio output ports.
CS8422 5.1 Serial Port Clock Operation 5.1.1 Master Mode When a serial port is set to master mode, its left/right clock (ILRCK, OLRCK1, or OLRCK2), and its serial bit-clock (ISCLK, OSCLK1, or OSCLK2) are outputs. If a serial output is sourced directly by the AES3 receiver, then that serial port’s left/right clock and serial bit-clock will be synchronous with RMCK.
CS8422 I/OLRCK Channel A Channel B I/OSCLK SDIN SDOUT M SB MSB LSB MSB LSB Figure 9. Serial Audio Interface Format – I²S I/OLRCK Channel A Channel B I/OSCLK SDIN SDOUT M SB LSB MSB MSB LSB Figure 10. Serial Audio Interface Format – Left-Justified I/OLRCK Channel A Channel B I/OSCLK SDIN SDOUT MSB Extended MSB LSB MSB LSB MSB Extended MSB LSB MSB LSB Figure 11.
CS8422 5.1.5 Time Division Multiplexing (TDM) Mode TDM Mode allows several TDM-compatible devices to be serially connected together allowing their corresponding serial output data to be multiplexed onto one line for input into a DSP or other TDM capable input device. In TDM Mode, the TDM_IN pin is used to input TDM-formatted data while the SDOUT1 or SDOUT2 (Software Mode only) pin is used to output TDM data. If the CS8422 is the first TDM device in the chain, it should have its TDM_IN connected to GND.
CS8422 OLRCK OSCLK SDOUT/ TDM_IN MSB MSB MSB MSB MSB MSB MSB MSB SDOUT 4, ch A SDOUT 4, ch B SDOUT 3, ch A SDOUT 3, ch B SDOUT 2, ch A SDOUT 2, ch B SDOUT 1, ch A SDOUT 1, ch B 32 OSCLKs 32 OSCLKs 32 OSCLKs 32 OSCLKs 32 OSCLKs 32 OSCLKs 32 OSCLKs 32 OSCLKs Data MSB LSB Figure 13.
CS8422 6. DIGITAL INTERFACE RECEIVER The CS8422 includes a digital interface receiver that can receive and decode audio data according to the AES3, IEC60958, S/PDIF, and EIJ CP1201 interface standards. The CS8422 uses either a 4:1 single-ended or 2:1 differential input mux to select the input pin(s) that will receive input data to be decoded. A low-jitter clock (RMCK) is recovered using a PLL, which provides the digital interface receiver with a master clock.
CS8422 6.2.2.1 Single-Ended Input Mode When the receiver input multiplexer is set to Single-Ended Mode, the receiver inputs can be switched between operation as comparator inputs or digital inputs. Receiver Input Mode 1 (Analog Sensitivity Mode) If Mode 1 is selected, the inputs are biased at VA/2 and should be coupled through a capacitor. The recommended value for the AC coupling capacitors is 0.01 µF to 0.1 µF. The recommended dielectrics for the AC coupling capacitors are C0G or X7R.
CS8422 VA (2 2 0 0 0 /N ) (2 2 0 0 0 /N ) R X N [1:0 ] (1 5 0 0 + 1 5 0 0 /N ) + R X P [1:0 ] - (1 5 0 0 + 1 5 0 0 /N ) (2 2 0 0 0 /N ) (2 2 0 0 0 /N ) AGND Note: 1. If RXP/N[1:0] is selected by either the receiver MUX or the TX pass-through MUX, N=1. 2. If RXP/N[1:0] is selected by both the receiver MUX and the TX pass-through MUX, N=2. 3. If RXP/N[1:0] is not selected at all, N=0 (i.e. high impedance). Figure 18. Differential Receiver Input Structure 6.
CS8422 frequencies will be derived from the XTI-XTO clock when clock switching has taken place and the RMCKto-LRCK ratio will be maintained. When clock switching is not enabled and the PLL has lost lock, RMCK will be derived from the VCO idle frequency. The frequency of the RMCK output will still be determined by the ratio selected by the RMCK[2:0] bits in register 09h, or the MS_SEL pin in Hardware Mode.
CS8422 The error bits are “sticky”, meaning that they are set on the first occurrence of the associated error and will remain set until the user reads the register through the control port. This enables the register to log all unmasked errors that occurred since the last time the register was read. As a result of the bits “stickiness”, it is necessary to perform two reads on these registers to see if the error condition still exists.
CS8422 If the AES3 stream contains sync codes in the proper format for IEC61937 or DTS® data transmission, an internal AUTODETECT signal will be asserted. If the sync codes no longer appear after a certain amount of time, auto-detection will time-out and AUTODETECT will be de-asserted until another format is detected. The AUDIO signal is the logical OR of AUTODETECT and the received channel status bit 1. In Software Mode AUDIO is available through the GPO pins.
CS8422 6.10.2 Software Mode Control In Software Mode, several options are available for accessing the Channel Status and User data that is encoded in the received AES3 or SPDIF data. The first option allows access directly through registers. The first 5 bytes of the Channel Status block are decoded into the “Channel Status Registers (23h - 2Ch)”. Registers 23h-27h contain the A channel status data. Registers 28h-2Ch contain the B channel status data.
CS8422 192 AES3 Frames RCBL (out) VLRCK (out) C/U (out) C/U[0] t Note: 1. 2. 3. 4. 5. 6. C/U[1] C/U[383] t RCBL will go high on the transition of the first output C/U data bit (C/U[0]) and will remain high until the C/U[0] - C/U[1] transition. VLRCK is a virtual word clock that is available through the GPO pins, and can be used to frame the C/U output. VLRCK frequency is always equal to the incoming frame rate of the AES3-compatible data.
CS8422 7. SAMPLE RATE CONVERTER (SRC) Multirate digital signal processing techniques are used to conceptually upsample the incoming data to a very high rate and then downsample to the outgoing rate. Internal filtering is designed so that a full input audio bandwidth of 20 kHz is preserved if the input sample and output sample rates are greater than or equal to 44.1 kHz.
CS8422 7.3 SRC Muting The SDOUT pin sourced by the SRC (SDOUT1 or SDOUT2 in Software Mode, SDOUT1 in Hardware Mode) is set to all zero output (full mute) immediately after the RST pin is set high. While the output from the SRC becomes valid, SDOUT will be soft unmuted over a period of approximately 27488/Fsi while in interpolation mode (Fsi < Fso) or 54976/Fso while in decimation mode (Fsi > Fso). When the output becomes invalid the SRC’s SDOUT is immediately set to all zero output (hard muted).
CS8422 oscillator provides the clock to run all of the internal logic. See Section 7.4.1 and Section 7.4.2 for explanation of how the SRC MCLK can be selected. 7.4.1 Hardware Mode Control In Hardware Mode, the default master clock source for the SRC is the internal ring oscillator. Therefore, it is not necessary to apply an external MCLK source for the SRC. Optionally the user may select the PLL clock as the SRC MCLK source by connecting a 20 k pull-up resistor between MCLK_OUT and VL. 7.4.
CS8422 2:1 MUX TX (MCLK_OUT Pull-up) (RMCK Pull-Up) MS_SEL SAOF TX_SEL Ring Oscillator RXP/RXN0 RXP/RXN1 2 2 2:1 M UX Sam ple Rate Converter 2:1 M UX Receiver Clock Recovery (PLL) 2:1 MUX Serial Audio Output 1 TDM _IN1 SDOUT1 OSCLK1 OLRCK1 Serial Audio Output 2 SDOUT2 OSCLK2 OLRCK2 MS_SEL SAOF RX_SEL RM CK Clock Generator MCLK_OUT XTI XTO Figure 21.
CS8422 Pin Name Description RX_SEL Selects Active AES3 RX Input TX_SEL Selects RX Input to be output on TX pin SDOUT1 Enables or Disables De-emphasis Auto-detect Pin Configuration Selection Connected to GND RXP0/RXN0 is active Connected to VL RXP1/RXN1 is active Connected to GND RXP0/RXN0 to TX Connected to VL RXP1/RXN1 to TX No pull-up on SDOUT1 De-emphasis Auto-detect Enabled 20 k pull-up on SDOUT1 De-emphasis Auto-detect Disabled SAOF Selects data format for SDOUT1 & SDOUT2 See T
CS8422 determines what the output sample rate will be based on the MCLK selected for SDOUT1, as shown in the hardware control pin descriptions shown above. For SDOUT2, the output sample rate is dictated by the incoming AES3 data, and the master mode clock ratio determines the frequency of RMCK relative to the incoming AES3 sample rate. Note: if TDM Mode is selected for SDOUT1, then SDOUT1 cannot be set to “Master, Fso = MCLK/128”. SAOF pin 32.4 k ± 1% to GND 16.2 k ± 1% to GND 8.06 k ± 1% to GND 4.
CS8422 9. SOFTWARE MODE CONTROL 9.1 Control Port Description The control port is used to access the registers, allowing the CS8422 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port has two modes: SPI and I²C, with the CS8422 acting as a slave device.
CS8422 9.1.2 I²C Mode In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There is no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should be connected to VL or DGND as desired. The GPO2 pin is used to set the AD2 bit by connecting a 20 k resistor from the GPO2 pin to VL (a 20 k pull-up sets AD2 = 1, and the absence of a pull-up sets AD2 = 0). The states of the pins are sensed after RST is released.
CS8422 10.REGISTER QUICK REFERENCE This table shows the register names and default values for read-write registers. Addr Function 01h Chip ID & Version 02h Clock Control 03h Receiver Input Control 04h Receiver Data Control 05h GPO Control 1 06h GPO Control 2 07h SAI Clock Control 08h SRC SAO Clock Control 09h RMCK Cntl.& Misc.
CS8422 Addr Function 7 6 5 4 3 2 1 0 11h Receiver Channel Status AUX3 AUX2 AUX1 AUX0 PRO COPY ORIG EMPH 12h Format Detect Status PCM IEC61937 DTS_LD DTS_CD HD_CD DGTL_SIL Reserved Reserved 13h Receiver Error Reserved QCRC CCRC UNLOCK V CONF BIP PAR 14h Interrupt Status PCCH OSLIP DETC CCH RERR QCH FCH SRC_ UNLOCK 15h PLL Status RX_ ACTIVE ISCLK_ ACTIVE PLL_LOCK 96KHZ 192KHZ Reserved Reserved Reserved 16h Receiver Status CS_ UPDATE RCVR_ RATE1 R
CS8422 Addr Function 7 6 5 4 3 2 1 0 2Ch Channel B Status Byte 4 BC4[7] BC4[6] BC4[5] BC4[4] BC4[3] BC4[2] BC4[1] BC4[0] 2Dh Burst Preamble PC Byte 0 PC0[7] PC0[6] PC0[5] PC0[4] PC0[3] PC0[2] PC0[1] PC0[0] Burst Preamble PC Byte 1 PC1[7] PC1[6] PC1[5] PC1[4] PC1[3] PC1[2] PC1[1] PC1[0] Burst Preamble Pd Byte 0 PD0[7] PD0[6] PD0[5] PD0[4] PD0[3] PD0[2] PD0[1] PD0[0] Burst Preamble PD Byte 1 PD1[7] PD1[6] PD1[5] PD1[4] PD1[3] PD1[2] PD1[1] PD1[0] 2Eh 2
CS8422 11.SOFTWARE REGISTER BIT DEFINITIONS The table row beneath the row that contains the register-bit name shows the register bit default value. Bits labeled ‘Reserved’ must remain at their default value. 11.1 CS8422 I.D. and Version Register (01h) 7 ID4 0 6 ID3 0 5 ID2 0 4 ID1 1 3 ID0 0 2 REV2 0 1 REV1 0 0 REV0 0 2 INT1 0 1 0 INT0 Reserved 0 0 ID[4:0] - ID code for the CS8422. Permanently set to 00010 REV[2:0] = 000 (revision A) REV[2:0] = 010 (revision B1) 11.
CS8422 01 - Active low, low output indicates an interrupt condition has occurred. 10 - Open drain, active low. Requires an external pull-up resistor on the INT pin. 11 - Reserved. 11.3 Receiver Input Control (03h) 7 RX_MODE 0 6 RXSEL1 0 5 RXSEL0 0 4 TXSEL1 1 3 TXSEL0 0 2 INPUT_TYPE 0 1 Reserved 0 0 Reserved 0 RX_MODE - Selects the input mode (single-ended or differential) of the RX pins 0 - Receiver inputs are differential-pair inputs RXP1/RXN1 and RXP0/RXN0.
CS8422 01 - replace the current audio sample with all zeros (mute). 10 - do not change the received audio sample. 11 - reserved CHS – Sets which channel's C data is decoded in the Receiver Channel Status register (11h) (Default = ‘0’) 0 - A channel 1 - B channel If CHS = 0 and TRUNC = 1, both channels' audio data will be truncated by the AUX[3:0] bits indicated in the channel A Channel Status data.
CS8422 11.5 GPO Control 1 (05h) 7 GPO0SEL3 0 6 GPO0SEL2 0 5 GPO0SEL1 0 4 GPO0SEL0 0 3 GPO1SEL3 0 2 GPO1SEL2 0 1 GPO1SEL1 0 0 GPO1SEL0 0 GPOxSEL[3:0] – GPO Source select for GPO0 and GPO1 pins. See Table 7 for available outputs for GPO[3:0]. 11.6 GPO Control 2 (06h) 7 GPO2SEL3 0 6 GPO2SEL2 0 5 GPO2SEL1 0 4 GPO2SEL0 0 3 GPO3SEL3 0 2 GPO3SEL2 0 1 GPO3SEL1 0 0 GPO3SEL0 0 GPOxSEL[3:0] – GPO Source select for GPO2 and GPO3 pins. See Table 7 for available outputs for GPO[3:0].
CS8422 0000 - ILRCK = MCLK/64 0001 - ILRCK = MCLK/96 0010 - ILRCK = MCLK/128 0011 - ILRCK = MCLK/192 0100 - ILRCK = MCLK/256 0101 - ILRCK = MCLK/384 0110 - ILRCK = MCLK/512 0111 - ILRCK = MCLK/768 1000 - ILRCK = MCLK/1024 SAI_MCLK – Selects the master clock (MCLK) source for the serial audio input when set to master mode (SIMS = 1, as shown in “Serial Audio Input Data Format (0Bh)” on page 54). When set to master, ILRCK and ISCLK are derived from the MCLK selected in this register.
CS8422 0 - XTI-XTO 1 - RMCK SRC_MCLK[1:0] - Controls the master clock (MCLK) source for the sample rate converter. See “SRC Master Clock” on page 38 for details. 00 - XTI-XTO. If XTI is connected to GND or VL and XTO is left floating, the SRC MCLK will be the internal ring oscillator. 01 - PLL clock 10 - Internal Ring Oscillator 11 - Reserved SRC_DIV – Divide-by-two for the SRC MCLK source. Valid only if SRC_MCLK = 00. 0 - SRC MCLK is not divided. Maximum allowable SRC MCLK frequency is 33 MHz.
CS8422 11.
CS8422 0000 64 64 INVALID 0001 96 48 96 0010 128 64 128 0011 192 48 96 0100 256 64 128 0101 384 48 96 0110 512 64 128 0111 768 48 96 1000 1024 64 128 Table 8. ISCLK/ILRCK Ratios and SISF Settings SIFSEL[2:0] - Serial audio input data format 000 - Left-Justified, up to 24-bit data 001 - I²S, up to 24-bit data 010 - Right-Justified, 24-bit data 011 - Right-Justified, 20-bit data 100 - Right-Justified, 18-bit data 101 - Right-Justified, 16-bit data 110, 111 - Reserved 11.
CS8422 0100 256 64 128 0101 384 48 96 0110 512 64 128 0111 768 48 96 1000 1024 64 128 Table 9. OSCLK1/OLRCK1 Ratios and SOSF1 Settings SORES1[1:0] - Resolution of the output data on SDOUT 00 - 24-bit resolution. 01 - 20-bit resolution. 10 - 18-bit resolution. 11 - 16-bit resolution SOFSEL1[1:0] - Format of the output data on SDOUT 00 - Left-Justified 01 - I²S 10 - Right-Justified (Master mode only) 11 - AES3 Direct.
CS8422 SAO_CLK[3:0], SAI_CLK[3:0], or RMCK[3:0] MCLK/OLRCK2 Ratio OSCLK2/OLRCK2 Ratio 0000 SOSF2 = 0 SOSF2 = 1 64 64 INVALID 0001 96 48 96 0010 128 64 128 0011 192 48 96 0100 256 64 128 0101 384 48 96 0110 512 64 128 0111 768 48 96 1000 1024 64 128 Table 10. OSCLK2/OLRCK2 Ratios and SOSF2 Settings SORES2[1:0] - Resolution of the output data on SDOUT 00 - 24-bit resolution. 01 - 20-bit resolution. 10 - 18-bit resolution.
CS8422 11.15 Interrupt Unmasking (0Fh) 7 PCCHM 0 6 OSLIPM 0 5 DETCM 0 4 CCHM 0 3 RERRM 0 2 QCHM 0 1 FCHM 0 0 SRC_UNLOCKM 0 The bits of this register serve as a mask for the Interrupt Status register. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the internal INT signal or the status register.
CS8422 1000 - Auxiliary data is 8 bits long. 1001 - 1111 Reserved PRO - Channel status block format indicator 0 - Received channel status block is in the consumer format. 1 - Received channel status block is in the professional format. COPY - SCMS copyright indicator 0 - Copyright asserted. 1 - Copyright not asserted. If the category code is set to General in the incoming AES3 stream, copyright will always be indicated by COPY, even when the stream indicates no copyright.
CS8422 interrupt mode is set to level active and the error source is still true. Bits that are masked off in the receiver error mask register will always be 0 in this register. QCRC - Q-subcode data CRC error indicator. Updated on Q-subcode block boundaries 0 - No error. 1 - Error. CCRC - Channel Status Block Cyclic Redundancy Check bit. Updated on CS block boundaries, valid only in Pro mode. 0 - No error. 1 - Error. UNLOCK - Receiver lock status when sourced by incoming AES3-compatible data.
CS8422 Indicates that the PC byte has changed from its previous value. If the IEC61937 bit in the Format Detect Status register goes high, it will cause a PCCH interrupt even if the PC byte hasn’t changed since the last time the IEC61937 bit went high. OSLIP - Serial audio output port data slip interrupt When the serial audio output port is in slave mode, and OLRCK is asynchronous to the port data source, this bit will go high every time a data sample is dropped or repeated.
CS8422 96KHZ – Indicates the frequency range of the sample rate of incoming AES3 data (Fsi). If Fsi 49 kHz or Fsi 120 kHz, this bit will output a “0”. If 60 kHz Fsi 98 kHz, this bit will output a “1”. Otherwise the output is indeterminate. 192KHZ – Indicates the frequency range of the sample rate of incoming AES3 data (Fsi). If Fsi 98 kHz, this bit will output a “0”. If Fsi 120 kHz, this bit will output a “1”. Otherwise the output is indeterminate. 11.
CS8422 1 - There has been at least one biphase error associated with incoming AES3 data during the input of the last AES3 data block. BLK_PERR - Block Parity Error. Updated on DETC boundaries 0 - There has been no parity error associated with incoming AES3 data during the input of the last AES3 data block. 1 - There has been at least one parity error associated with incoming AES3 data during the input of the last AES3 data block. 11.
CS8422 Each byte is MSB first with respect to the 80 Channel Status bits. Thus bit 0 of address 23h, AC0[0], is the location of the Pro bit. For N = 0-79, Channel Status bit N (per AES specification) is mapped to bit N mod 8 (remainder of N divided by 8) at address 23h+floor(N/8) (23h + integer result of N divided by 8 rounded down). For example, Channel Status bit 35 is mapped to bit 3 (35/8 = 4 remainder 3) of address 27h (23h + 4h). 11.
CS8422 12.APPLICATIONS 12.1 Reset, Power Down, and Start-Up When RST is low the CS8422 enters a low power mode, all internal states are reset, and the outputs are disabled. After RST transitions from low to high the part senses the resistor value on the configuration pins (MS_SEL and SAOF) and sets the appropriate mode of operation. After the mode has been set (approximately 4 s) the part is set to normal operation and all outputs are functional. 12.
CS8422 boxes held to the same potential, and the cable shield might be depended upon to make that electrical connection. Generally, it is a good idea to provide the option of grounding or capacitively coupling the shield to the chassis. XLR CS8422 * See Text RXP 110 Twisted Pair 110 XLR CS8422 0.01 F * See Text RXP0 110 Twisted Pair 110 0.01 F RXN0 RXN 1 1 Figure 26. Professional Input Circuit – Differential Mode .01F 75 Coax 75 Coax 75 CS8422 RX3 RX2 .. .
CS8422 + Vin - .01F R1 75 Coax CS8422 RX R2 AGND 247.5 Vin (1) R2 = (2) R1 = 75 – R2 Figure 32. Receiver Input Attenuation – Single-ended Input Vin+ Vin- CS8422 Rin RXP 110 Twisted Pair Rin R RXN AGND (1) R = 726 Vin+ - Vin- (2) Rin = 55 - R 2 Figure 33. Receiver Input Attenuation – Differential Input 12.3.2 Isolating Transformer Requirements Please refer to the application note AN134: AES and SPDIF Recommended Transformers for resources on transformer selection 12.
CS8422 There are a number of conditions that will inhibit the buffer update. If the CS_UPDATE bit in “Receiver Status (16h)” is set to ‘0’, the only condition that will inhibit the update is PLL phase unlock. If the CS_UPDATE bit in “Receiver Status (16h)” is set to ‘1’, a biphase, confidence, parity, or CRC error will also inhibit the update. A 8-bits From AES3 Receiver Received Data Buffer E B 8-bits 5 words Control Port Registers 24 words D C Data Serial Output Figure 34.
CS8422 12.4.3 Serial Copy Management System (SCMS) In Software Mode, the CS8422 allows read access to all the channel status bits. For consumer mode SCMS compliance, the host microcontroller needs to read and interpret the Category Code, Copy bit and L bit appropriately. In Hardware Mode, the SCMS protocol can be followed by using the C bit serial output pin. See “Channel Status and User Data Handling” on page 34 for more details. 12.
CS8422 12.6 Jitter Tolerance The CS8422 is compliant to the jitter tolerance requirements set forth in the AES-3 and IEC60958-4 specifications. Figure 37 shows the receiver jitter tolerance template as illustrated in the AES3 and IEC60958-4 specifications along with the measured tolerance of the CS8422. Figure 37. Jitter Tolerance Template 12.7 Group Delay The group delay introduced by the CS8422 depends on the type of interface selected, and input and output sample rates of the sample rate converter.
CS8422 13.PERFORMANCE PLOTS Test conditions (unless otherwise specified): Measurement bandwidth is 20 Hz to Fso/2 Hz (unweighted); VA = VL = V_REG = 3.3 V; XTI - XTO = 24.
CS8422 +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 -70 -70 -80 d B F S -80 -90 d B F S -100 -110 -90 -1 00 -1 10 -120 -1 20 -130 -1 30 -140 -1 40 -150 -1 50 -160 -1 60 -170 -1 70 -180 -1 80 -1 90 -190 -200 -2 00 2.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k 5k 22.5k Figure 44.
CS8422 +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 -70 -70 -80 d B F S -80 -90 d B F S -1 00 -1 10 -90 -1 00 -1 10 -1 20 -1 20 -1 30 -1 30 -1 40 -1 40 -1 50 -1 50 -1 60 -1 60 -1 70 -1 70 -1 80 -1 80 -1 90 -1 90 -2 00 2. 5k 5k 7 .5 k 1 0k 12 .5 k 1 5k 1 7. 5k 2 0k -2 00 22 .5 k 2 .5k 5k 7 .5 k 10 k Hz Figure 50.
CS8422 +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 -70 -70 -80 d B F S -80 -90 d B F S -1 00 -1 10 -90 -1 00 -1 10 -1 20 -1 20 -1 30 -1 30 -1 40 -1 40 -1 50 -1 50 -1 60 -1 60 -1 70 -1 70 -1 80 -1 80 -1 90 -1 90 -2 00 10 k 2 0k 3 0k 4 0k 50 k 6 0k 70 k 8 0k -2 00 90 k 5k 1 0k 1 5k 2 0k Hz Figure 56.
CS8422 +0 +0 -1 0 -1 0 -2 0 -2 0 -3 0 -3 0 -4 0 -4 0 -5 0 -5 0 -6 0 -6 0 -7 0 -7 0 -8 0 -8 0 -9 0 -9 0 d B F S d B F S -1 0 0 -1 0 0 -1 1 0 -1 1 0 -1 2 0 -1 2 0 -1 3 0 -1 3 0 -1 4 0 -1 4 0 -1 5 0 -1 5 0 -1 6 0 -1 6 0 -1 7 0 -1 7 0 -1 8 0 -1 8 0 -1 9 0 -1 9 0 -2 0 0 -2 0 0 40k 60k 80k 100k 120k 140k 160k 180k 40k 60k 80k 100k 120k Figure 62. THD+N vs.
CS8422 +0 +0 -1 0 -1 0 -2 0 -2 0 -3 0 -3 0 -4 0 -4 0 -5 0 -5 0 -6 0 -6 0 -7 0 -7 0 -8 0 -8 0 -9 0 d B F S -9 0 d B F S -1 0 0 -1 1 0 -1 2 0 -1 1 0 -1 2 0 -1 3 0 -1 3 0 -1 4 0 -1 4 0 -1 5 0 -1 5 0 -1 6 0 -1 6 0 -1 7 0 -1 7 0 -1 8 0 -1 8 0 -1 9 0 -2 0 0 -1 0 0 -1 9 0 40k 60k 80k 100k 120k 140k 160k -2 0 0 180k 40k 60k 80k 100k Hz +5 T 120k 140k 160k 180k Hz Figure 68. Dynamic Range vs. Output Sample Rate – -60 dBFS 1 kHz Tone, Fsi = 96 kHz T Figure 69.
CS8422 +0 +0 -5 -5 -1 0 -1 0 -1 5 -1 5 -2 0 -2 0 -2 5 -2 5 -3 0 -3 0 -3 5 -3 5 -4 0 -4 0 -4 5 -4 5 -5 0 -5 0 -5 5 -5 5 -6 0 d B F S -6 0 -6 5 d B F S -7 0 -7 5 -6 5 -7 0 -7 5 -8 0 -8 0 -8 5 -8 5 -9 0 -9 0 -9 5 -9 5 -1 0 0 -1 0 0 -1 0 5 -1 0 5 -1 1 0 -1 1 0 -1 1 5 -1 1 5 -1 2 0 -1 2 0 -1 2 5 -1 2 5 -1 3 0 -1 3 0 -1 3 5 -1 4 0 -1 4 0 -1 3 5 -1 2 0 -1 0 0 -8 0 -6 0 -4 0 -2 0 -1 4 0 -1 4 0 +0 -1 2 0 -1 0 0 -8 0 dB FS -5 -1 0 -1 5 -1 5 -2 0 -2
CS8422 -1 0 0 -1 0 0 -1 0 5 -1 0 5 -1 1 0 -1 1 0 -1 1 5 -1 1 5 -1 2 0 -1 2 0 -1 2 5 -1 2 5 -1 3 0 -1 3 0 -1 3 5 d B F S -1 3 5 d B F S -1 4 0 -1 4 0 -1 4 5 -1 4 5 -1 5 0 -1 5 0 -1 5 5 -1 5 5 -1 6 0 -1 6 0 -1 6 5 -1 6 5 -1 7 0 -1 7 0 -1 7 5 -1 7 5 -1 8 0 -1 4 0 -1 2 0 -1 0 0 -8 0 -6 0 -4 0 -2 0 -1 8 0 -1 4 0 +0 -1 2 0 -1 0 0 -8 0 dB FS -1 1 0 -1 1 5 -1 1 5 -1 2 0 -1 2 0 -1 2 5 -1 2 5 -1 3 0 -1 3 0 -1 3 5 -1 3 5 d B F S -1 4 0 -1 4 5 -1 4 0 -1 4 5 -1
CS8422 -1 0 0 -1 0 0 -1 0 5 -1 0 5 -1 1 0 -1 1 0 -1 1 5 -1 1 5 -1 2 0 -1 2 0 -1 2 5 -1 2 5 -1 3 0 -1 3 0 -1 3 5 -1 3 5 d B F S d B F S -1 4 0 -1 4 0 -1 4 5 -1 4 5 -1 5 0 -1 5 0 -1 5 5 -1 5 5 -1 6 0 -1 6 0 -1 6 5 -1 6 5 -1 7 0 -1 7 0 -1 7 5 -1 7 5 -1 8 0 -1 8 0 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 0 2k 4k 6k 8k Figure 86. THD+N vs. Input Frequency – 0 dBFS, 48 kHz:44.
CS8422 14.PACKAGE DIMENSIONS 32L QFN (5 X 5 mm BODY) PACKAGE DRAWING e b D Pin #1 Corner Pin #1 Corner E2 E A1 L D2 A Top View DIM MIN A A1 b D D2 E E2 e L -0.0000 0.0079 0.1437 0.1437 0.0118 Bottom View Side View INCHES NOM --0.0098 0.1969 BSC 0.1457 0.1969 BSC 0.1457 0.0197 BSC 0.0157 MAX MIN 0.0394 0.0020 0.0118 -0.00 0.20 0.1476 3.65 0.1476 3.65 0.0197 0.30 MILLIMETERS NOM --0.25 5.00 BSC 3.70 5.00 BSC 3.70 0.50 BSC 0.40 NOTE MAX 1.00 0.05 0.30 3.75 3.75 0.
CS8422 16.ORDERING INFORMATION Product CS8422 CDB8422 Description Package Pb-Free 24-bit, Asynchronous Sample Rate Converter with Integrated Digital Interface Receiver QFN YES Evaluation Board for CS8422 - YES Grade Temp Range Container Order# Rail CS8422-CNZ Commercial -40° to +85°C Tape and Reel CS8422-CNZR - - - CDB8422 17.REFERENCES 1.
CS8422 18.REVISION HISTORY Release Changes F1 Final Release. Changed VA, VREG, and VL = 5.0 V normal operation values in DC Electrical Characteristics table. Updated Figure 37 with test data from CS8422. Updated Figure 90. Updated hardware mode NVERR and RERR descriptions in Section 6.6.2 Hardware Mode Control. Updated values in Switching Specifications table. Added TDM_IN pin not supported in master mode in Switching Specifications table and Section 5.1.5.1. Updated Section 11.
