Owner manual

8 DS245F4
CS8420
DIGITAL INPUT CHARACTERISTICS
DIGITAL INTERFACE SPECIFICATIONS
AGND = DGND = 0 V; all voltages with respect to 0 V.
TRANSMITTER CHARACTERISTICS
SWITCHING CHARACTERISTICS
Inputs: Logic 0 = 0 V, Logic 1 = VD+; C
L
= 20 pF.
5. Cycle-to-cycle jitter using 32-96 kHz external PLL components.
6. PLL is bypassed (RXD1:0 bits in the Clock Source Control register set to 10b), clock is input to the RMCK
pin.
Parameters Symbol Min Typ Max Units
Input Leakage Current I
in
-±10±15μA
Differential Input Voltage, RXP to RXN V
TH
200 - - mVpp
Parameters Symbol Min Max Units
High-Level Output Voltage (I
OH
= -3.2 mA), except TXP/TXN V
OH
(VD+) - 1.0 - V
Low-Level Output Voltage (I
OH
= 3.2 mA), except TXP/TXN V
OL
-0.4V
High-Level Output Voltage (I
OH
= -21 mA), TXP, TXN (VD+) - 0.7 - V
Low-Level Output Voltage (I
OH
= 21 mA), TXP, TXN - 0.7 V
High-Level Input Voltage, except RXP, RXN V
IH
2.0 (VD+) + 0.3 V
Low-Level Input Voltage, except RXP, RXN V
IL
-0.3 0.8 V
Parameters Symbol Typ Units
TXP Output Resistance R
TXP
25 Ω
TXN Output Resistance R
TXN
25 Ω
Parameter Symbol Min Typ Max Units
RST
pin Low Pulse Width 200 - - μs
OMCK Frequency for OMCK = 512 * Fso 4.096 - 55.3 MHz
OMCK Low and High Width for OMCK = 512 * Fso 8.2 - - ns
OMCK Frequency for OMCK = 384 * Fso 3.072 - 41.5 MHz
OMCK Low and High Width for OMCK = 384 * Fso 12.3 - - ns
OMCK Frequency for OMCK = 256 * Fso 2.048 - 27.7 MHz
OMCK Low and High Width for OMCK = 256 * Fso 16.4 - - ns
PLL Clock Recovery Sample Rate Range 8.0 - 108.0 kHz
RMCK output jitter (Note 5) -200-ps RMS
RMCK output duty cycle 40 50 60 %
RMCK Input Frequency (Note 6) 2.048 - 27.7 MHz
RMCK Input Low and High Width (Note 6) 16.4 - - ns
AES3 Transmitter Output Jitter - - 1 ns