Owner manual

DS245F4 71
CS8420
13.6 Hardware Mode 5 Description
(AES3 Receiver Only)
Hardware Mode 5 data flow is shown in Figure 28. Audio data is input via the AES3 receiver, and routed to
the serial audio output port. The PRO, COPY, ORIG, EMPH
, and AUDIO channel status bits are output on
pins. The decoded C and U bits are also output, clocked by both edges of OLRCK (Master mode only, see
Figure 19).
If a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample is passed unmodified
to the serial audio output port.
Start-up options are shown in Table 14, and allow choice of the serial audio output port as a master or slave,
and the serial audio port format. The following pages contain the detailed pin descriptions for Hardware
mode 5.
SDOUT ORIG EMPH
Function
LO - - Serial Output Port is Slave
HI - - Serial Output Port is Master
- LO LO Serial Output Format OF1
- LO HI Serial Output Format OF2
- HI LO Serial Output Format OF3
- HI HI Serial Output Format OF5
Table 14. Hardware Mode 5 Start-Up Options
Serial
Audio
Output
AES3 Rx
&
Decoder
C&UbitDataBuffer
RXP
RXN
OLRCK
OSCLK
SDOU
T
RMCK RERR
COPY ORIG EMPH RCBLPRO AUDIO
CHS
DFC0 DFC1 S/AES
VD+
H/S
Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT)
are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
VD+VD+
NVERR
C
U
OMCK
Figure 28. Hardware Mode 5 - AES3 Receiver Only