CS8420 Digital Audio Sample Rate Converter Features General Description Complete IEC60958, AES3, S/PDIF, EIAJ The CS8420 is a stereo digital audio sample rate converter (SRC) with AES3-type and serial digital audio inputs, AES3-type and serial digital audio outputs, and includes comprehensive control ability via a 4-wire microcontroller port. Channel status and user data can be assembled in block-sized buffers, making read/modify/write cycles easy.
CS8420 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 SPECIFIED OPERATING CONDITIONS .............................................................................................. 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6 PERFORMANCE SPECIFICATIONS .........................................................................
CS8420 10.13 Interrupt Register 2 Mode Registers MSB & LSB (0Dh,0Eh) ..................................................... 42 10.14 Receiver Channel Status (0Fh) (Read Only) ............................................................................. 43 10.15 Receiver Error (10h) (Read Only) .............................................................................................. 44 10.16 Receiver Error Mask (11h) ........................................................................................
CS8420 16. PLL FILTER ........................................................................................................................................ 87 16.1 General ........................................................................................................................................ 87 16.2 External Filter Components ......................................................................................................... 87 16.2.1 General .........................................
CS8420 Figure 35.Consumer Input Circuit ............................................................................................................. 80 Figure 36.TTL/CMOS Input Circuit ............................................................................................................ 80 Figure 37.Channel Status Data Buffer Structure ....................................................................................... 81 Figure 38.Channel Status Block Handling When Fso is Not Equal to Fsi .......
CS8420 1. CHARACTERISTICS AND SPECIFICATIONS All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C. SPECIFIED OPERATING CONDITIONS AGND, DGND = 0 V, all voltages with respect to 0 V. Parameter Power Supply Voltage Ambient Operating Temperature: Commercial Grade Automotive Grade Symbol Min Typ Max Units VD+, VA+ 4.
CS8420 PERFORMANCE SPECIFICATIONS Parameter* Symbol Dynamic Range Min Typ Max Units 120 128 - dB Fsi 8 - 108 kHz Fso 8 - 108 kHz 0.33 - 3 - - -117 -112 -110 -107 dB dB dB dB - - -140 dBFS Resolution 16 - 24 bits Gain Error -0.12 - 0 dB Input Sample Rate (serial input port) Output Sample Rate Output to Input Sample Rate Ratio THD+N Total Harmonic Distortion + Noise 1 kHz, -1 dBFS, 0.33 < Fso/Fsi < 1.7 1 kHz, -1 dBFS, 0.33 < Fso/Fsi < 3 10 kHz, -1 dBFS, 0.
CS8420 DIGITAL INPUT CHARACTERISTICS Parameters Input Leakage Current Differential Input Voltage, RXP to RXN Symbol Min Typ Max Units Iin - ±10 ±15 μA VTH 200 - - mVpp DIGITAL INTERFACE SPECIFICATIONS AGND = DGND = 0 V; all voltages with respect to 0 V. Parameters Symbol Min Max Units High-Level Output Voltage (IOH = -3.2 mA), except TXP/TXN VOH (VD+) - 1.0 - V Low-Level Output Voltage (IOH = 3.2 mA), except TXP/TXN VOL - 0.
CS8420 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS Inputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF.
CS8420 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ MODE Inputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF. Parameter Symbol Min Typ Max Units fsck 0 - 6.0 MHz CS High Time Between Transmissions tcsh 1.
CS8420 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C® MODE Inputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF. Parameter Symbol Min Typ Max Units SCL Clock Frequency fscl - - 100 kHz Bus Free Time Between Transmissions tbuf 4.7 - - μs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - - μs Clock Low Time tlow 4.7 - - μs Clock High Time thigh 4.0 - - μs Setup Time for Repeated Start Condition tsust 4.
CS8420 2. TYPICAL CONNECTION DIAGRAM +5V Analog Supply * Ferrite * Bead VA+ AES3/ SPDIF Source Cable Termination +5V Digital Supply 0.1μF 0.
CS8420 3. GENERAL DESCRIPTION The CS8420 is a fully asynchronous sample rate converter plus AES3 transceiver intended to be used in digital audio systems. Such systems include digital mixing consoles, effects processors, tape recorders, and computer multimedia systems. The CS8420 is intended for 16-, 20-, and 24-bit applications where the input sample rate is unknown, or is known to be asynchronous to the system sample rate. On the input side of the CS8420, AES3 or 3-wire serial format can be chosen.
CS8420 4. DATA I/O FLOW AND CLOCKING OPTIONS The CS8420 can be configured for nine connectivity alternatives, referred to as data flows. Each data flow has an associated clocking set-up. Figure 6 shows the data flow switching, along with the control register bits which control the switches. This drawing only shows the audio data paths for simplicity. Figure 7 shows the internal clock routing and the associated control register bits.
CS8420 The AESBP switch allows a TTL level, bi-phase mark-encoded data stream connected to RXP to be routed to the TXP and TXN pin drivers. The TXOFF switch causes the TXP and TXN outputs to be driven to ground In modes including the SRC function, there are two audio-data-related clock domains. One domain includes the input side of SRC, plus the attached data source. The second domain includes the output side of the SRC, plus any attached output ports. There are two possible clock sources.
CS8420 Serial Audio Output SDIN ISCLK ILRCK Serial Audio Input Sample Rate Converter AES3 Encoder & Driver PLL RMCK OLRCK OSCLK SDOUT TXP RMCK Clock Source Control Bits OUTC: 0 INC: 0 RXD1-0: 00 Serial Audio Output RXP Sample Rate Converter AES3 Encoder & Driver PLL OLRCK OSCLK SDOUT TXP AES3 Encoder & Driver TXP TXN Clock Source Control Bits OUTC: 0 INC: 0 RXD1-0: 10 Figure 9.
CS8420 SDOUT OSCLK OLRCK SDIN ISCLK ILRCK Serial Serial Audio Audio Output Input RXN RXP RXN RXP AES3 Rx & Decode AES3 Encoder & Driver AES3 Rx & Decode Serial Audio Output OLRCK OSCLK SDOUT TXP PLL TXN PLL RMCK RMCK Data Flow Control Bits TXD1-0: 01 SPD1-0: 10 SRCD: 0 Data Flow Control Bits TXD1-0: 10 SPD1-0: 10 SRCD: 0 TXOFF: 1 Clock Source Control Bits OUTC: 1 INC: 0 RXD1-0: 01 Figure 14.
CS8420 5. SAMPLE RATE CONVERTER (SRC) Multirate digital signal processing techniques are used to conceptually upsample the incoming data to very high rate and then downsample to the outgoing rate, resulting in a 24-bit output, regardless of the width of the input. The filtering is designed so that a full input audio bandwidth of 20 kHz is preserved if the input sample and output sample rates are greater than 44.1 kHz.
CS8420 6. THREE-WIRE SERIAL AUDIO PORTS A 3-wire serial audio input port and a 3-wire serial audio output port is provided. Each port can be adjusted to suit the attached device via control registers. The following parameters are adjustable: master or slave, serial clock frequency, audio data resolution, left or right justification of the data relative to left/right clock, optional 1-bit cell delay of the 1st data bit, the polarity of the bit clock and the polarity of the left/right clock.
CS8420 ILRCK Left Justified (In) Channel A ISCLK SDIN MSB LSB ILRCK I²S (In) Channel B MSB LSB Channel A MSB Channel B ISCLK SDIN MSB ILRCK Right Justified (In) MSB LSB MSB LSB Channel A Channel B ISCLK SDIN MSB LSB MSB LSB SIMS SISF SIRES1/0 SIJUST SIDEL SISPOL SILRPOL Left-Justified X X 00 0 0 0 0 I²S X X 00+ 0 1 0 1 0 0 0 Right-Justified X X XX* 1 X = don’t care to match format, but does need to be set to the desired setting + I²S can accept an arbitra
CS8420 OLRCK Left Justified OSCLK (Out) SDOUT Channel A LSB MSB OLRCK I²S (Out) MSB LSB Channel A MSB Channel B OSCLK SDOUT LSB MSB OLRCK Right Justified OSCLK (Out) SDOUT AES3 Direct (Out) Channel B MSB Channel A MSB Extended OLRCK Channel B MSB Extended LSB MSB Channel B Channel A MSB LSB MSB LSB Channel A Channel B OSCLK SDOUT LSB MSB V U C LSB MSB V U C LSB MSB V U C Z LSB MSB V U C Z Frame 0 Frame 191 SOMS SOSF SORES1/0 SOJUST SODEL SOSPOL SOLRPOL Left
CS8420 7. AES3 TRANSMITTER AND RECEIVER The CS8420 includes an AES3-type digital audio receiver and an AES3-type digital audio transmitter. A comprehensive buffering scheme provides read/write access to the channel status and user data. This buffering scheme is described in “Channel Status and User Data Buffer Management” on page 81. 7.1 AES3 Receiver The AES3 receiver accepts and decodes audio and digital data according to the AES3, IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards.
CS8420 7.1.4 Channel Status Data Handling The first 2 bytes of the Channel Status block are decoded into the Receiver Channel Status register. The setting of the CHS bit in the Channel Status Data Buffer Control register determines whether the channel status decodes are from the A channel (CHS = 0) or B channel (CHS = 1). The PRO (professional) bit is extracted directly.
CS8420 7.1.6 Non-Audio Auto Detection Since it is possible to convey non-audio data in an AES3 data stream, it is important to know whether the incoming AES3 data stream is digital audio or other data. This information is typically conveyed in channel status bit 1 (AUDIO), which is extracted automatically by the CS8420. However, certain non-audio sources, such as AC-3® or MPEG encoders, may not adhere to this convention, and the bit may not be properly set.
CS8420 7.2.2 TXN and TXP Drivers The line drivers are low-skew, low-impedance, differential outputs capable of driving cables directly. Both drivers are set to ground during reset (RST = low), when no AES3 transmit clock is provided, and optionally under the control of a register bit. The CS8420 also allows immediate mute of the AES3 transmitter audio data via a control register bit. External components are used to terminate and isolate the external cable from the CS8420.
CS8420 Tth TCBL In or Out VLRCK Tsetup Thold VCU Input VCU[0] SDIN Input TXP(N) Data[4] Z VCU[1] Data[5] Data[0] Y Data[1] VCU[2] Data[6] X Data[2] VCU[3] Data[7] Y Data[3] AES3 Transmitter in Stereo Mode TCBL In or Out Tth VCU[4] Data[8] X Data[4] Tsetup = > 7.
CS8420 TRANSMITTER STEREO MODE RECEIVER STEREO MODE 96kHz Fsi 96kHz stereo 96kHz frame rate AES3 Receiver A A B B PLL In 96kHz Fso SRC Out A A B AES3 B Transmitter OMCK (256, 384, or 512x 96kHz) 256x96kHz TRANSMITTER MONO MODE RECEIVER MONO MODE 96kHz Fsi 96kHz mono 48kHz frame rate A AES3 Receiver 96kHz stereo 96kHz frame rate * B A In 96kHz Fso SRC A A + B PLL (x2) Out 96kHz mono 48kHz frame rate MMTLR B AES3 B Transmitter 256x96kHz OMCK (256, 384, or 512x 96kHz) * A
CS8420 8. 8.1 AES3 TRANSMITTER AND RECEIVER Sample Rate Converter The equation for the group delay through the sample rate converter, with the serial ports in Master mode is: ((input interface delay + 43) / Fsi) + ((43 + output interface delay ± 0.5) / Fso) The unit of delay depends on the frame rate (sample rate) Fs. The AES receiver has a interface delay of 2 frames. The AES transmitter, the serial input port, and the serial output port each have an interface delay of 1 frame. The ± 0.
CS8420 8.2 Non-SRC Delay The unit of delay depends on the frame rate (sample rate) Fs. The AES receiver has a interface delay of two frames. The AES transmitter, the serial input port, and the serial output port each have an interface delay of 1 frame. The ± 0.5 frame delay in the second half of the equation is due to the startup uncertainty of the logic within the part. 1. All inputs are slaves and all outputs are masters, both with respect to the outside world. 2.
CS8420 9. CONTROL PORT DESCRIPTION AND TIMING The control port is used to access the registers, allowing the CS8420 to be configured for the desired operational modes and formats. In addition, Channel Status and User data may be read and written via the control port. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required.
CS8420 9.2 I²C Mode In I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 23. There is no CS pin. Each individual CS8420 is given a unique address. Pins AD[1:0] form the two least significant bits of the chip address and should be connected to VD+ or DGND as desired. The EMPH pin is used to set the AD2 bit, by connecting a resistor from the EMPH pin to VD+ or to DGND.
CS8420 10. CONTROL PORT REGISTER BIT DEFINITIONS 10.1 Memory Address Pointer (MAP) 7 INCR 6 MAP6 5 MAP5 4 MAP4 3 MAP3 2 MAP2 1 MAP1 0 MAP0 This register defaults to 01 INCR Auto-Increment Address Control Bit 0Auto-increment address off 1Auto-increment address on MAP6-MAP0 Register address and function list 0Reserved 1Misc. Control 1 2Misc.
CS8420 Addr (HEX) 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14-1D 1E 20-37 7F Function 7 Control 1 Control 2 Data Flow Control Clock Source Control Serial Input Format Serial Output Format Interrupt 1 Status Interrupt 2 Status Interrupt 1 Mask Interrupt 1 Mode (MSB) Interrupt 1 Mode (LSB) Interrupt 2 Mask Interrupt 2 Mode (MSB) Interrupt 2 Mode (LSB) Receiver CS Data Receiver Errors Receiver Error Mask CS Data Buffer Control U Data Buffer Control Q Sub-Code Data Sample Rate Ratio C or U D
CS8420 10.2 Miscellaneous Control 1 (01h) 7 SWCLK 6 VSET 5 MUTESAO 4 MUTEAES 3 DITH 2 INT1 1 INT0 0 TCBLD SWCLK Causes OMCK to be output through the RMCK pin when the PLL is unlocked 0 - RMCK is driven by the PLL VCO (default) 1 - OMCK is switched to output through the RMCK pin when the PLL is unlocked. Circuitry driven by the PLL is driven by OMCK.
CS8420 10.3 Miscellaneous Control 2 (02h) 7 TRUNC 6 HOLD1 5 HOLD0 4 RMCKF 3 MMR 2 MMT 1 MMTCS 0 MMTLR TRUNC Determines whether the word length is set according to the incoming Channel Status data 0 - Data to the SRC is not truncated (default) 1 - Data to the SRC is set according to the AUX field in the incoming data stream HOLD[1:0] The HOLD bits determine how the received audio sample is affected when a receiver error occurs.
CS8420 10.4 Data Flow Control (03h) 7 AMLL 6 TXOFF 5 AESBP 4 TXD1 3 TXD0 2 SPD1 1 SPD0 0 SRCD The Data Flow Control register configures the flow of audio data to/from the following blocks: Serial Audio Input Port, Serial Audio Output Port, AES3 receiver, AES3 transmitter, and Sample Rate Converter. In conjunction with the Clock Source Control register, multiple Receiver/Transmitter/Transceiver modes may be selected.
CS8420 10.5 Clock Source Control (04h) 7 0 6 RUN 5 CLK1 4 CLK0 3 OUTC 2 INC 1 RXD1 0 RXD0 This register configures the clock sources of various blocks. In conjunction with the Data Flow Control register, various Receiver/Transmitter/Transceiver modes may be selected. RUN The RUN bit controls the internal clocks, allowing the CS8420 to be placed in a “powered down”, low current consumption, state. 0 - Internal clocks are stopped. Internal state machines are reset.
CS8420 10.
CS8420 10.
CS8420 10.8 Interrupt 1 Register Status (07h) (Read Only) 7 TSLIP 6 OSLIP 5 SRE 4 OVRGL 3 OVRGR 2 DETC 1 EFTC 0 RERR For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register was last read. A”0” means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true.
CS8420 10.9 Interrupt Register 2 Status (08h) (Read Only) 7 6 5 4 3 2 1 0 0 0 VFIFO REUNLOCK DETU EFTU QCH UOVW For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register was last read. A”0” means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true.
CS8420 10.12 Interrupt 2 Register Mask (0Ch) 7 0 6 0 5 VFIFOM 4 REUNLOCKM 3 DETUM 2 EFTUM 1 QCHM 0 UOVWM The bits of this register serve as a mask for the Interrupt 2 Register. If a mask bit is set to 1, the error is considered unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is considered masked, meaning that its occurrence will not affect the INT pin or the status register.
CS8420 10.14 Receiver Channel Status (0Fh) (Read Only) 7 AUX3 6 AUX2 5 AUX1 4 AUX0 3 PRO 2 AUDIO 1 COPY 0 ORIG The bits in this register can be associated with either channel A or B of the received data. The desired channel is selected with the CHS bit of the Channel Status Data Buffer Control Register. AUX[3:0] The AUX3-0 bits indicate the width of the incoming auxiliary data field, as indicated by the incoming channel status bits, decoded according to IEC60958 and AES3.
CS8420 10.15 Receiver Error (10h) (Read Only) 7 0 6 QCRC 5 CCRC 4 UNLOCK 3 V 2 CONF 1 BIP 0 PAR This register contains the AES3 receiver and PLL status bits. Unmasked bits will go high on occurrence of the error, and will stay high until the register is read. Reading the register resets all bits to 0, unless the error source is still true. Bits that are masked off in the receiver error mask register will always be 0 in this register. This register defaults to 00.
CS8420 10.16 Receiver Error Mask (11h) 7 0 6 QCRCM 5 CCRCM 4 UNLOCKM 3 VM 2 CONFM 1 BIPM 0 PARM The bits in this register serve as masks for the corresponding bits of the Receiver Error Register. If a mask bit is set to 1, the error is considered unmasked, meaning that its occurrence will appear in the receiver error register, will affect the RERR pin, will affect the RERR interrupt, and will affect the current audio sample according to the status of the HOLD bit.
CS8420 10.18 User Data Buffer Control (13h) 7 0 6 0 5 0 4 UD 3 UBM1 2 UBM0 1 DETUI 0 EFTUI UD User data pin (U) direction specifier 0 - The U pin is an input. The U data is latched in on both rising and falling edges of OLRCK. This setting also chooses the U pin as the source for transmitted U data (default). 1 - The U pin is an output. The received U data is clocked out on both rising and falling edges of ILRCK. This setting also chooses the U data buffer as the source of transmitted U data.
CS8420 10.19 Sample Rate Ratio (1Eh) (Read Only) 7 SRR7 6 SRR6 5 SRR5 4 SRR4 3 SRR3 2 SRR2 1 SRR1 0 SRR0 The Sample Rate Ratio is Fso divided by Fsi. This value is represented as an integer and a fractional part. The value is meaningful only after the both the PLL and SRC have reached lock, and the SRC output is being used SRR[7:6 The integer part of the sample rate ratio SRR[5:0] The fractional part of the sample rate ratio 10.
CS8420 11. SYSTEM AND APPLICATIONS ISSUES 11.1 Reset, Power Down and Start-up Options When RST is low, the CS8420 enters a low-power mode. All internal states are reset, including the control port and registers, and the outputs are muted. When RST is high, the control port becomes operational, and the desired settings should be loaded into the control registers. Writing a 1 to the RUN bit will then cause the part to leave the low-power state and begin operation.
CS8420 11.3 SRC Invalid State Occasionally the CS8420 SRC will enter an invalid state. This can happen after the RUN bit has been set when an AES3 stream is first plugged into the part or when a source device interrupts the SRC input stream. When this happens, two symptoms may be noticeable: notches occurring in the frequency response and spurious tones being generated in response to some input frequencies.
CS8420 11.5 Block-Mode U-Data D-to-E Buffer Transfers When Fsi ≠ Fso, Block-Mode U-data transfers from the D buffer to the E buffer are not synchronous to the input clock domain. D-to-E buffer transfers can always be detected by the activation of the DETU bit (bit 3 in register 08h) when Fsi ≠ Fso or Fsi = Fso. IEC Consumer B mode, serial U-data output, and the Qchannel subcode bytes (registers 14h - 1Dh) are unaffected by the input/output sample rate relationship. 11.
CS8420 12. SOFTWARE MODE - PIN DESCRIPTION The above diagram and the following pin descriptions apply to Software mode. In Hardware mode, some pins change their function as described in subsequent sections of this data sheet. Fixed function pins are marked with a *, and will be described once in this section. Pins marked with a + are used upon reset to select various start-up options, and require a pull-up or pull-down resistor.
CS8420 FILT - PLL Loop Filter * An RC network should be connected between this pin and ground. Recommended schematic and component values are given in “PLL Filter” on page 87. Overall Device Control: H/S - Hardware or Software Control Mode Select * The H/S pin determines the method of controlling the operation of the CS8420, and the method of accessing CS and U data. In Software mode, device control and CS and U data access is primarily via the control port, using a microcontroller.
CS8420 EMPH - Pre-Emphasis Indicator Output EMPH is low when the incoming AES3 data indicates the presence of 50/15 μs pre-emphasis. When the AES3 data indicates the absence of pre-emphasis or the presence of other than 50/15 μs pre-emphasis EMPH is high. This is also a start-up option pin, and requires a 47 kΩ resistor to either VD+ or DGND, which determines the AD2 address bit for the control port in I²C mode.
CS8420 Miscellaneous Pins: U - User Data The U pin may optionally be used to input User data for transmission by the AES3 transmitter (see Figure 20 for timing information). Alternatively, the U pin may be set to output User data from the AES3 receiver (see Figure 19 for timing information). If not driven, a 47 kΩ pull-down resistor is recommended for the U pin since the default state of the UD direction bit sets the U pin as an input.
CS8420 13. HARDWARE MODES 13.1 Overall Description The CS8420 has six Hardware modes, which allow use of the device without using a micro-controller to access the device control registers and CS & U data. The flexibility of the CS8420 is necessarily limited in Hardware mode. Various pins change function in Hardware mode, and various data paths are also possible. These alternatives are identified by Hardware mode numbers 1 through 6.
CS8420 13.2 Hardware Mode 1 Description (DEFAULT Data Flow, AES3 Input) Hardware Mode 1 data flow is shown in Figure 24. Audio data is input via the AES3 receiver, and rate converted. The audio data at the new rate is then output both via the serial audio output port and via the AES3 transmitter. The channel status data, user data and validity bit information are handled in four alternative modes: 1A and 1B, determined by a start-up resistor on the COPY pin.
CS8420 13.2.1 Pin Description - Hardware Mode 1 Overall Device Control: DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, as shown in Table 5. S/AES - Serial Audio or AES3 Input Select S/AES is connected to ground in Hardware mode 1 in order to select the AES3 input. MUTE - Mute Output Data Input If MUTE is low, audio data is passed normally.
CS8420 RERR - Receiver Error Indicator When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once per sub-frame of incoming AES3 data. Conditions that cause RERR to go high are: parity error, and bi-phase coding error, as well as loss of lock in the PLL. This is also a start-up option pin, and requires a pull-up or pull-down resistor.
CS8420 13.3 Hardware Mode 2 Description (DEFAULT Data Flow, Serial Input) Hardware Mode 2 data flow is shown in Figure 25. Audio data is input via the serial audio input port, and rate converted. The audio data at the new rate is then output both via the serial audio output port and via the AES3 transmitter. The C, U, and V bits in the AES3 output stream may be set in two methods, selected by the CUVEN pin.
CS8420 COPY/C ORIG/U 0 0 1 1 0 1 0 1 Function PRO=0, COPY=0, L=0 PRO=0, COPY=0, L=1 PRO=0, COPY=1, L=0 PRO=1 Table 9. HW Mode 2A COPY/C and ORIG/U Pin Function SFMT1 SFMT0 0 0 1 1 0 1 0 1 Function Serial Input & Output Format IF1&OF1 Serial Input & Output Format IF2&OF2 Serial Input & Output Format IF3&OF3 Serial Input & Output Format IF4&OF3 Table 10.
CS8420 13.3.1 Pin Description - Hardware Mode 2 Overall Device Control: DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table 5. S/AES - Serial Audio or AES3 Input Select S/AES is connected to VD+ in Hardware mode 2, in order to select the serial audio input. SFMT0, SFMT1 - Serial Audio Port Data Format Select Inputs SFMT0 and SFMT1 select the serial audio input and output ports’ format. See Table 10.
CS8420 RMCK - Input Section Recovered Master Clock Output Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi). LOCK - PLL Lock Indicator Output LOCK low indicates that the PLL is locked. This is also a start-up option pin, and requires a pull-up or pull-down resistor. Audio Output Interface: SDOUT - Serial Audio Output Port Data Output Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor.
CS8420 13.4 Hardware Mode 3 Description (Transceive Data Flow, with SRC) Hardware Mode 3 data flow is shown in Figure 26. Audio data is input via the AES3 receiver, and rate converted. The audio data at the new rate is then output via the serial audio output port. Different audio data, synchronous to OMCK, may be input into the serial audio input port, and output via the AES3 transmitter.
CS8420 SDOUT RMCK RERR ORIG COPY Function LO Serial Output Port is Slave HI Serial Output Port is Master LO Mode 3A: C transmitted data is copied from received data, U & V =0, received PRO, EMPH, AUDIO is visible HI Mode 3B: CUV transmitted data is input serially on pins, received PRO, EMPH and AUDIO is not visible LO LO Serial Input & Output Format IF1&OF1 LO HI Serial Input & Output Format IF2&OF2 HI LO Serial Input & Output Format IF3&OF3 HI HI Serial Input & Output Format IF2&OF4 LO TCBL is an input HI
CS8420 13.4.1 Pin Description - Hardware Mode 3 Overall Device Control: DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table 5. OMCK - Output Section Master Clock Input Output section master clock input. The frequency must be 256x the output sample rate (Fso). Audio Input Interface: SDIN - Serial Audio Input Port Data Input Audio data serial input pin. This data will be transmitted out the AES3 port.
CS8420 OLRCK - Serial Audio Output Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso). AES3/SPDIF Transmitter Interface: TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state.
CS8420 13.5 Hardware Mode 4 Description (Transceive Data Flow, No SRC) Hardware mode 4 data flow is shown in Figure 27. Audio data is input via the AES3 receiver, and routed to the serial audio output port. Different audio data synchronous to RMCK may be input into the serial audio input port, and output via the AES3 transmitter. The channel status data, user data, and validity bit information are handled in two alternative modes: 4A and 4B, determined by a start-up resistor on the COPY pin.
CS8420 SDOUT RMCK RERR ORIG COPY Function LO Serial Output Port is Slave HI Serial Output Port is Master LO Mode 4A: C transmitted data is copied from received data, U & V =0, received PRO, EMPH, AUDIO is visible HI Mode 4B: CUV transmitted data is input serially on pins, received PRO, EMPH and AUDIO is not visible LO LO Serial Input & Output Format IF1&OF1 LO HI Serial Input & Output Format IF2&OF2 HI LO Serial Input & Output Format IF3&OF3 HI HI Serial Input & Output Format IF1&OF5 LO TCBL is an input HI
CS8420 13.5.1 Pin Description - Hardware Mode 4 Overall Device Control: DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table 5. Audio Input Interface: SDIN - Serial Audio Input Port Data Input Audio data serial input pin. This data will be transmitted out the AES3 port. ISCLK - Serial Audio Input Port Bit Clock Input or Output Serial bit clock for audio data on the SDIN pin.
CS8420 OSCLK - Serial Audio Output Port Bit Clock Input or Output Serial bit clock for audio data on the SDOUT pin. OLRCK - Serial Audio Output Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDOUT pin. The frequency will be at the input sample rate (Fsi). AES3/SPDIF Transmitter Interface: TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state.
CS8420 13.6 Hardware Mode 5 Description (AES3 Receiver Only) Hardware Mode 5 data flow is shown in Figure 28. Audio data is input via the AES3 receiver, and routed to the serial audio output port. The PRO, COPY, ORIG, EMPH, and AUDIO channel status bits are output on pins. The decoded C and U bits are also output, clocked by both edges of OLRCK (Master mode only, see Figure 19).
CS8420 13.6.1 Pin Description - Hardware Mode 5 Overall Device Control: DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table 5. S/AES - Serial Audio or AES3 Input Select S/AES is connected to DGND in Hardware mode 5, in order to select the AES3 input. OMCK - Output Section Master Clock Input Output section master clock input. This pin is not used in this mode and should be connected to DGND.
CS8420 AES3/SPDIF Receiver Interface: RXP, RXN - Differential Line Receiver Inputs Differential line receiver inputs, carrying AES3 type data. RMCK - Input Section Recovered Master Clock Output Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi). RERR - Receiver Error Indicator When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once per sub-frame of incoming AES3 data.
CS8420 13.7 Hardware Mode 6 Description (AES3 Transmitter Only) Hardware Mode 6 data flow is shown in Figure 29. Audio data is input via the serial audio input port and routed to the AES3 transmitter. The transmitted channel status, user, and validity data may be input in two alternative methods, determined by the state of the CEN pin. Mode 6A is selected when the CEN pin is low. In mode 6A, the user data and validity bit are input via the U and V pins, clocked by both edges of ILRCK.
CS8420 COPY/C ORIG 0 0 1 1 0 1 0 1 Function PRO=0, COPY=0, L=0 PRO=0, COPY=0, L=1 PRO=0, COPY=1, L=0 PRO=1 Table 15. HW 6 COPY/C and ORIG Pin Function SFMT1 SFMT0 0 0 1 1 0 1 0 1 Function Serial Input Format IF1 Serial Input Format IF2 Serial Input Format IF3 Serial Input Format IF4 Table 16.
CS8420 13.7.1 Pin Description - Hardware Mode 6 COPY/C DFC0 EMPH SFMT0 SFMT1 VA+ AGND FILT RST APMS TCBLD ILRCK ISCLK SDIN 1 2 3 4 5 6* 7* 8* 9* 10 11 12 13 14 28 27 26 25 *24 *23 *22 21 20 19 18 17 16 15 ORIG DFC1 TXP TXN H/S VD+ DGND OMCK S/AES AUDIO U V CEN TCBL * Pins which remain the same function in all modes. Overall Device Control: DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table 5.
CS8420 ILRCK - Serial Audio Input Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDIN pin. APMS - Serial Audio Input Port Master or Slave. APMS should be connected to VD+ to set serial audio input port as a master, or connected to DGND to set the port as a slave. AES3/SPDIF Transmitter Interface: TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state.
CS8420 14. EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER AND RECEIVER COMPONENTS This section details the external components required to interface the AES3 transmitter and receiver to cables and fiber-optic components. 14.1 AES3 Transmitter External Components The output drivers on the CS8420 are designed to drive both the professional and consumer interfaces. The AES3 specification for professional/broadcast use calls for a 110 Ω source impedance and a balanced drive capability.
CS8420 The TXP pin may be used to drive TTL or CMOS gates as shown in Figure 32. This circuit may be used for optical connectors for digital audio since they usually have TTL or CMOS compatible inputs. This circuit is also useful when driving multiple digital audio outputs since RS422 line drivers have TTL compatible inputs. CS8420 TXP TTL or CMOS Gate TXN Figure 32. TTL/CMOS Output Circuit 14.
CS8420 connection. Generally, it may be a good idea to provide the option of grounding or capacitively coupling the shield to the chassis. In the case of the consumer interface, the standards call for an unbalanced circuit having a receiver impedance of 75 Ω ±5%. The connector for the consumer interface is an RCA phono socket. The receiver circuit for the consumer interface is shown in Figure 35. 0.01 μF RCA Phono CS8420 RXP 75 Ω 75 Ω Coax RXN 0.01 μF Figure 35.
CS8420 15. CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT The CS8420 has a comprehensive channel status (C) and user (U) data buffering scheme, which allows automatic management of channel status blocks and user data. Alternatively, sufficient control and access is provided to allow the user to completely manage the C and U data via the control port. 15.
CS8420 15.1.1 Manually Accessing the E Buffer The user can monitor the data being transferred by reading the E buffer, which is mapped into the register space of the CS8420, via the control port. The user can modify the data to be transmitted by writing to the E buffer.
CS8420 . E to F interrupt occurs Optionally set E to F inhibit Set D to E inhibit Write E data If set, clear E to F inhibit Wait for E to F transfer Clear D to E inhibit Return Figure 40. Flowchart for Writing the E Buffer 15.1.2 Reserving the First 5 Bytes in the E Buffer D-to-E buffer transfers periodically overwrite the data stored in the E buffer. This can be a problem for users who want to transmit certain channel status settings which are different from the incoming settings.
CS8420 15.1.5 One-Byte Mode In many applications, the channel status blocks for the A and B channels will be identical. In this situation, if the user reads a byte from one of the channel's blocks, the corresponding byte for the other channel will be the same. Similarly, if the user wrote a byte to one channel's block, it would be necessary to write the same byte to the other block. One-Byte mode takes advantage of the often identical nature of A and B channel status data.
CS8420 transmitted bit. The first byte read is the first byte received, and the first byte sent is the first byte transmitted. 15.2.3 IEC60958 Recommended U Data Format for Consumer Applications Modes (3) and (4) are intended for use in AES3 in, AES3 out situations, in which the input U data is formatted as recommended in the “IEC60958 Digital Audio Interface, part 3: Consumer applications” document. In this format, “messages” are formed in the U data from Information Units or IUs.
CS8420 transmitter can read out data that had previously accumulated, allowing the FIFO to empty out. If the FIFO becomes completely empty, zeros are transmitted until a complete message is written into the FIFO. Mode 4 is not fail-safe; the FIFO can still get completely full if there isn't enough “zero-padding” between incoming messages.
CS8420 16. PLL FILTER 16.1 General An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream. Figure 41 is a simplified diagram of the PLL in CS8420 devices. When the PLL is locked to an AES3 input stream, it is updated at each preamble in the AES3 stream. This occurs at twice the sampling frequency, FS. When the PLL is locked to ILRCK, it is updated at FS so that the duty cycle of the input doesn’t affect jitter.
CS8420 16.2.2 Capacitor Selection The type of capacitors used for the PLL filter can have a significant effect on receiver performance. Large or exotic film capacitors are not necessary as their leads and the required longer circuit board traces add undesirable inductance to the circuit. Surface mount ceramic capacitors are a good choice because their own inductance is low, and they can be mounted close to the FILT pin to minimize trace inductance.
CS8420 16.3.2 Locking to the RXP/RXN Receiver Inputs CS8420 parts that are configured to lock to only the RXP/RXN receiver inputs should use the external PLL component values listed in Table 18 and Table 19. Values listed for the 32 to 96 kHz Fs range will have the highest corner frequency jitter attenuation curve, take the shortest time to lock, and offer the best output jitter performance. Revision RFILT (kΩ) CFILT (μF) CRIP (nF) PLL Lock Time (ms) D 0.909 1.8 33 56 D1 0.4 0.
CS8420 16.3.4 Jitter Tolerance Shown in Figure 43 is the Receiver Jitter Tolerance template as illustrated in the AES3 and IEC60958-4 specification. CS8420 parts used with the appropriate external PLL component values (as noted in Table 19) have been tested to pass this template. Figure 43. Jitter Tolerance Template 16.3.
CS8420 17. PARAMETER DEFINITIONS Input Sample Rate (Fsi) The sample rate of the incoming digital audio. Input Frame Rate The frame rate of the received AES3 format data. Output Sample Rate (Fso) The sample rate of the outgoing digital audio. Output Frame Rate The frame rate of the transmitted AES3 format data. Dynamic Range The ratio of the maximum signal level to the noise floor. Total Harmonic Distortion and Noise The ratio of the noise and distortion to the test signal level.
CS8420 18. PACKAGE DIMENSIONS 28L SOIC (300 MIL BODY) PACKAGE DRAWING E H 1 b c ∝ D L SEATING PLANE A e A1 INCHES DIM MIN MAX A A1 B C D E e H L 0.093 0.004 0.013 0.009 0.697 0.291 0.040 0.394 0.016 0° 0.104 0.012 0.020 0.013 0.713 0.299 0.060 0.419 0.050 8° ∝ MILLIMETERS MIN MAX 2.35 0.10 0.33 0.23 17.70 7.40 1.02 10.00 0.40 0° 2.65 0.30 0.51 0.32 18.10 7.60 1.52 10.65 1.
CS8420 19. ORDERING INFORMATION Product Description Package Pb-Free No CS8420 Digital Audio Sample 28-SOIC Rate Converter Grade Temp Range Commercial -10º to +70ºC Commercial -10º to +70ºC Yes Automotive -40º to +85ºC CDB8420 Evaluation Board for CS8420 - - - Container Order# Rail CS8420-CS Tape and Reel CS8420-CSR Rail CS8420-CSZ Tape and Reel CS8420-CSZR Rail CS8420-DSZ Tape and Reel CS8420-DSZR - - CDB8420 20.
CS8420 Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied).
