User guide

DS578F3 55
CS8416
18.2.5 Jitter Attenuation
Shown in Figure 25 is the jitter attenuation plot. The AES3 and IEC60958-4 specifications state a maxi-
mum of 2 dB jitter gain or peaking.
10
1
10
0
10
1
10
2
10
3
10
4
10
5
12
10
8
6
4
2
0
2
4
J itte r F re que ncy (H z )
externa l J itte r Attenuation ( dB )
Figure 25. Jitter Attenuation Characteristics of PLL