User guide

10 DS578F3
CS8416
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(Inputs: Logic 0 = 0 V, Logic 1 = VL; C
L
= 20 pF)
Notes:
12. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is dic-
tated by the timing requirements necessary to access the Channel Status memory. Access to the con-
trol register file can be carried out at the full 6 MHz rate. The minimum allowable input sample rate is
32 kHz, so choosing CCLK to be less than or equal to 4.1 MHz should be safe for all possible conditions.
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For f
sck
<1 MHz.
Parameter Symbol Min Max Unit
CCLK Clock Frequency (Note 12) f
sck
06.0MHz
CS
High Time Between Transmissions t
csh
1.0 - µs
CS
Falling to CCLK Edge t
css
20 - ns
CCLK Low Time t
scl
66 - ns
CCLK High Time t
sch
66 - ns
CDIN to CCLK Rising Setup Time t
dsu
40 - ns
CCLK Rising to DATA Hold Time (Note 13) t
dh
15 - ns
CCLK Falling to CDOUT Stable t
pd
-50ns
Rise Time of CDOUT t
r1
-25ns
Fall Time of CDOUT t
f1
-25ns
Rise Time of CCLK and CDIN (Note 14) t
r2
-100ns
Fall Time of CCLK and CDIN (Note 14) t
r2
-100ns
t
r2
t
f2
t
dsu
t
dh
t
sch
t
scl
CS
CCLK
CDIN
t
css
t
pd
CDOUT
t
csh
Figure 3. SPI Mode Timing