CS8406 192 kHz Digital Audio Interface Transmitter Features General Description Complete EIAJ CP1201, IEC-60958, AES3, The CS8406 is a monolithic CMOS device which encodes and transmits audio data according to the AES3, IEC60958, S/PDIF, o r EIAJ CP1201 standards. The CS8406 accepts aud io and digital data, which is then multiplexed, encoded, and driven onto a cable. S/PDIF-compatible Transmitter +3.3 V or 5.0 V Digital Supply (VD) +3.3 V or 5.
CS8406 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 4 SPECIFIED OPERATING CONDITIONS .............................................................................................. 4 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 4 DC ELECTRICAL CHARACTERISTICS .......................................................................
CS8406 15. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER COMPONENTS ................... 35 15.1 AES3 Transmitter External Components .................................................................................... 35 15.2 Isolating Transformer Requirements .......................................................................................... 35 16. APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT ........................ 36 16.1 AES3 Channel Status(C) Bit Management ................
CS8406 1. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C.) SPECIFIED OPERATING CONDITIONS (GND = 0 V, all voltages with respect to 0 V) Parameter Symbol Min Typ Max Units VD VL 3.14 3.14 3.3 or 5.0 3.3 or 5.0 5.25 5.
CS8406 DIGITAL INPUT CHARACTERISTICS Parameters Symbol Min Iin Input Leakage Current Input Hysteresis (all inputs except OMCK) Typ Max Units - - ±0.5 A - 0.25 - V DIGITAL INTERFACE SPECIFICATIONS (GND = 0 V; all voltages with respect to 0 V.) Parameters Symbol Min Max Units High-Level Output Voltage (IOH = -3.2 mA), except TXP/TXN VOH VL - 1.0 - V Low-Level Output Voltage (IOH = 3.2 mA), except TXP/TXN VOL - 0.4 V High-Level Output Voltage, TXP, TXN (21 mA at VL = 5.
CS8406 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS (Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF) Parameter Symbol Min Typ Max Units SDIN Setup Time Before ISCLK Active Edge (Note 5) tds 10 - - ns SDIN Hold Time After ISCLK Active Edge (Note 5) tdh 8 - - ns OMCK to ISCLK active edge delay (Note 5) tsmd 0 - 17 ns OMCK to ILRCK delay (Note 6) tlmd 0 - 16 ns - 50 - % Master Mode ISCLK and ILRCK Duty Cycle Slave Mode ISCLK Period tsckw 36 - - ns ISCLK Input Lo
CS8406 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF) Parameter Symbol Min Typ Max Units fsck 0 - 6.0 MHz CS High Time Between Transmissions tcsh 1.
CS8406 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE (Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF) Parameter Symbol Min Typ Max Units SCL Clock Frequency fscl - - 100 kHz Bus Free Time Between Transmissions tbuf 4.7 - - s Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - - s Clock Low Time tlow 4.7 - - s Clock High Time thigh 4.0 - - s Setup Time for Repeated Start Condition tsust 4.
CS8406 2. TYPICAL CONNECTION DIAGRAMS +3.3 V or +5.0 V +3.3 V or +5.0 V 0.1 F 0.1 F VD AES3 / S/PDIF Source RXP Serial Audio Source ILRCK ISCLK SDIN Clock Source and Control Microcontroller CS8406 VL TXP TXN Transmission Interface OMCK AD0 / CS AD1 / CDIN AD2 SCL / CCLK SDA / CDOUT U 47k User Data Source H/S RST INT TCBL GND To/from other CS8406's Figure 5.
CS8406 +3.3 V or +5.0 V +3.3 V or +5.0 V 0.1 F 0.1 F VD Serial Audio Source Clock Source and Control Hardware Control H/S ILRCK ISCLK SDIN OMCK HWCK1 HWCK0 SFMT0 SFMT1 APMS TCBLD RST CEN EMPH AUDIO ORIG TCBL VL CS8406 TXP TXN Transmission Interface C Data Source COPY/C U 47k V 47k User Data Source Validity Source GND To/from other CS8406's Figure 6.
CS8406 3. GENERAL DESCRIPTION The CS8406 is a monolithic CMOS device which encodes a nd transmits audio data according to the AES3, IEC60958, S/PDIF, and EIAJ CP1201 interface standards. The CS8406 accepts audio, channel status and user data, which is then multiplexed, encoded, and driven onto a cable. The audio data is input through a configurable, 3-wire input port.
CS8406 4. THREE-WIRE SERIAL INPUT AUDIO PORT A 3-wire serial audio input port is provided. The interface format can be adjusted to suit the attached device through the control registers.
CS8406 5. AES3 TRANSMITTER The CS8406 includes an AES3 digital audio transmitter. A comprehensive buffering scheme provides write access to the channel status and user data. This buffering scheme is described in “Appendix B: Channel Status and User Data Buffer Management” on page 36. The AES3 transmitter encodes and transmits audio and digital data according to the AES3, IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. Audio and control data are multiplexed together and bi-phase mark encoded.
CS8406 a) With TCBL set to input, driving TCBL high for >3 OMCK clocks will cause a frame start, as well as a new channel status block start. b) If the serial audio input port is in Slave Mode and TCBL is set to output, the start of the A channel subframe will be aligned with the leading edge of ILRCK. The timing of TCBL, VLRCK, C, U, and V are illustrated in Figure 8 and Figure 9. VLRCK is the internal virtual word clock signal, and is used here only to illustrate the timing of the C, U, and V bits.
CS8406 TCBL Tth VLRCK U U[0] Data [4] SDIN TXP(N) Z Data [5] Data [0]* U[2] Data [6] Data [7] Data [8] Y Data [2]* X Data [4]* Y Data [3]* X Data [5]* * Assume MMTLR = 0 TXP(N) Z Data [1]* * Assume MMTLR = 1 Note: 1. Tsetup 15% AES3 frame rate 2. Thold = 0 3. Tth > 3 OMCKS if TCBL is an input Figure 9.
CS8406 6. CONTROL PORT DESCRIPTION The control port is used to access the registers, allowing the CS8406 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port has two modes: SPI and I²C, with the CS8406 acting as a slave device.
CS8406 6.2 I²C Mode In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There is no CS pin. Pins AD0, AD1, and AD2 form the three least significant bits of the chip address and should be connected to VL or GND as desired. The signal timing for both a read and write cycle are shown in Figure 11 and Figure 12. A Start condition is defined as a falling transition of SDA while the clock is high.
CS8406 7.
CS8406 8. CONTROL PORT REGISTER BIT DEFINITIONS 8.1 Memory Address Pointer (MAP) Not a register 7 0 6 MAP6 5 MAP5 4 MAP4 3 MAP3 2 MAP2 1 MAP1 0 MAP0 MAP[6:0] - Memory Address Pointer. Will automatically increment after each read or write. 8.
CS8406 MMTCS - Select A or B channel status data to transmit in Mono Mode Default = ‘0’ 0 - Use channel A CS data for the A subframe and use channel B CS data for the B subframe 1 - Use the same CS data for both the A and B subframe outputs. If MMTLR = 0, use the left channel CS data. If MMTLR = 1, use the right channel CS data.
CS8406 Default = ‘00’ 00 - OMCK frequency is 256*Fs 01 - OMCK frequency is 384*Fs 10 - OMCK frequency is 512*Fs 11 - OMCK frequency is 128*Fs 8.
CS8406 8.7 Interrupt 1 Status (07h) (Read Only) 7 TSLIP 6 0 5 0 4 0 3 0 2 0 1 EFTC 0 0 For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since the register was last read. A ‘0’ me ans the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to ‘0’, unless the Interrupt Mode is set to level and the interrupt source is still true.
CS8406 8.10 Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB (0Bh) 7 TSLIP1 TSLIP0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 EFTC1 EFTC0 0 0 0 The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin becomes active on the arrival of the interrupt condition.
CS8406 Note: There are separate complete buffers for the Channel Status and User bits. This control bit determines which buffer appears in the address space. EFTCI - E to F C-data buffer transfer inhibit bit. Default = ‘0’ 0 - Allow C-data E to F buffer transfers 1 - Inhibit C-data E to F buffer transfers CAM - C-data buffer control port access mode bit Default = ‘0’ 0 - One-Byte Mode 1 - Two-Byte Mode 8.
CS8406 9. PIN DESCRIPTION - SOFTWARE MODE SDA / CDOUT 1 28 SCL / CCLK AD0 / CS 2 27 AD1 / CDIN AD2 3 26 TXP RXP 4 25 TXN TSTN 5 24 H/S VD 6 23 VL TEST 7 22 GND TEST 8 21 OMCK RST 9 20 U TEST 10 19 INT TEST 11 18 TEST ILRCK 12 17 TEST ISCLK 13 16 TEST SDIN 14 15 TCBL VD 6 Digital Power (Input) - Digital core power supply. Typically +3.3 V or +5.0 V. VL 23 Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V.
CS8406 SDA/CDOUT 1 Serial Control Data I/O (I²C Mode) / Data Out (SPI) (Input/Output) - In I²C Mode, SDA is the control I/O data line. SDA is open drain and requires an external pull-up resistor to VL. In SPI Mode, CDOUT is the output data from the control port interface on the CS8406 SCL/CCLK 28 Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and out of the CS8406. In I²C Mode, SCL requires an external pull-up resistor to VL.
CS8406 10.HARDWARE MODE The CS8406 has a Hardware Mode that allows the use of the device without a microcontroller. Hardware Mode is selected by connecting the H/S pin to VL. The flexibility of the CS8406 is necessarily limited in Hardware Mode. Various pins change function as described in the Hardware Mode pin description section. The Hardware Mode data flow is shown in Figure 13. Audio data is input through the serial audio input port and routed to the AES3 transmitter. 10.
CS8406 The channel status block pin (TCBL) may be an input or an output, determined by the state of the TCBLD pin. COPY/C 0 0 1 1 ORIG 0 1 0 1 Function PRO=0, COPY=0, L=0 copyright PRO=0, COPY=0, L=1 copyright, pre-recorded PRO=0, COPY=1, L=0 non-copyright PRO=1 Table 2. Hardware Mode COPY/C and ORIG Pin Functions 10.2 Serial Audio Port The serial audio input port data format is selected as shown in Table 3, and may be set to master or slave by the state of the APMS input pin.
CS8406 11.PIN DESCRIPTION - HARDWARE MODE COPY / C 1 28 ORIG TEST 2 27 HWCK1 EMPH 3 26 TXP SFMT0 4 25 TXN SFMT1 5 24 H/S VD 6 23 VL TEST 7 22 GND TEST 8 21 OMCK RST 9 20 HWCK0 APMS 10 19 AUDIO TCBLD 11 18 U ILRCK 12 17 V ISCLK 13 16 CEN SDIN 14 15 TCBL VD 6 Digital Power (Input) - Digital core power supply. Typically +3.3 V or +5.0 V. VL 23 Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V.
CS8406 SFMT0 SFMT1 4 5 Serial Audio Data Format Select (Input) - Selects the serial audio input port format. See Table 3 on page 28. APMS 10 Serial Audio Data Port Master/Slave Select (Input) - APMS should be connected to VL to set serial audio input port as a master or connected to GND to set the port as a slave. HWCK0 HWCK1 20 27 OMCK Clock Ratio Select (Input) - Selects the ratio of OMCK to the input sample rate (Fs). A pull-up to VL or pull-down to GND is required to set the appropriate mode.
CS8406 12.APPLICATIONS 12.1 Reset, Power Down and Start-Up When RST is low, the CS8406 enters a low power mode and all internal states are reset, including the control port and registers, and the outputs are disabled. In Software Mode when RST is high, the control port becomes operational and the desired settings should be loaded into the control registers. Writing a 1 to the RUN bit will then cause the part to leave the low power state and begin operation.
CS8406 13.PACKAGE DIMENSIONS 28L SOIC (300 MIL BODY) PACKAGE DRAWING E 1 H b c D L SEATING PLANE A e DIM A A1 b C D E e H L µ A1 MIN 0.093 0.004 0.013 0.009 0.697 0.291 0.040 0.394 0.016 0° INCHES NOM 0.098 0.008 0.017 0.011 0.705 0.295 0.050 0.407 0.026 4° MAX 0.104 0.012 0.020 0.013 0.713 0.299 0.060 0.419 0.050 8° MIN 2.35 0.10 0.33 0.23 17.70 7.40 1.02 10.00 0.40 0° MILLIMETERS NOM 2.50 0.20 0.42 0.28 17.90 7.50 1.27 10.34 0.65 4° MAX 2.65 0.30 0.51 0.32 18.10 7.60 1.52 10.65 1.
CS8406 28L TSSOP (4.4 mm BODY) PACKAGE DRAWING N D E11 A2 E e b2 SIDE VIEW A A1 END VIEW L SEATING PLANE 1 2 3 TOP VIEW INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A -- -- 0.47 -- -- 1.20 A1 0.002 0.004 0.006 0.05 0.10 0.15 A2 0.03150 0.035 0.04 0.80 0.90 1.00 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 D 0.378 BSC 0.382 BSC 0.386 BSC 9.60 BSC 9.70 BSC 9.80 BSC 1 E 0.248 0.2519 0.256 6.30 6.40 6.50 E1 0.169 0.1732 0.177 4.30 4.
CS8406 14.
CS8406 15.APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER COMPONENTS This section details the external components required to interface the AES3 transmitter to cables and fiber-optic components. 15.1 AES3 Transmitter External Components The output drivers on the CS8406 are designed to drive both the professional and consumer interfaces. The AES3 and IEC60958-4 specifications call for a balanced output drive of 2-7 V peak-to-peak into a 110 ± 20% load with no cable attached.
CS8406 16.APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT The CS8406 has a comprehensive channel status (C) and user (U) data buffering scheme which allows the user to manage the C and U data through the control port. 16.1 AES3 Channel Status(C) Bit Management The CS8406 contains sufficient RAM to store a full block of C data for both A and B channels (192x2 = 384 bits), and also 384 bits of U information. The user may read from or write to these RAM buffers through the control port.
CS8406 troller. This is also true if the channel status data is entered serially through the COPY/C pin when the part is in Hardware Mode. E to F interrupt occurs Optionally set E to F inhibit Write E data If set, clear E to F inhibit Wait for E to F transfer Return Figure 18. Flowchart for Writing the E Buffer 16.1.2 Serial Copy Management System (SCMS) In Software Mode, the CS8406 allows read/modify/write access to all the channel status bits.
CS8406 16.1.3.2 Two-Byte Mode There are those applications in which the A and B channel status blocks will not be the same, and the user is interested in accessing both blocks. In these situations, Two-Byte Mode should be used to access the E buffer. In this mode, a read will cause the CS 8406 to output two bytes from its control port. The first byte out will represent the A channel status data, and the 2nd byte will represent the B channel status data.
CS8406 17.REVISION HISTORY Release Date Changes F3 July 2005 -Updated Packaging Information to include Lead Free devices and updated “Table of Contents” on page 2. F4 April 2006 -Removed references to “Autoincrement” feature in “Control Port Description” on page 16. Indicated that the MAP will always increment. -Corrected definition of pin 5 in “Pin Description - Software Mode” on page 25.
