User Manual
Table Of Contents
- Features
- Description
- 1. Pin Out - 144-Pin LQFP Package
- 2. Pin Out - 160-Ball FBGA Package
- 3. Pin Descriptions
- 4. operation
- 5. Power-up
- 6. Master Clock
- 7. G.772 Monitoring
- 8. Building Integrated Timing Systems (BITS) Clock Mode
- 9. Transmitter
- 10. Receiver
- 11. Jitter Attenuator
- 12. Operational Summary
- 13. Host Mode
- 14. Register Descriptions
- 14.1 Revision/IDcode Register (00h)
- 14.2 Analog Loopback Register (01h)
- 14.3 Remote Loopback Register (02h)
- 14.4 TAOS Enable Register (03h)
- 14.5 LOS Status Register (04h)
- 14.6 DFM Status Register (05h)
- 14.7 LOS Interrupt Enable Register (06h)
- 14.8 DFM Interrupt Enable Register (07h)
- 14.9 LOS Interrupt Status Register (08h)
- 14.10 DFM Interrupt Status Register (09h)
- 14.11 Software Reset Register (0Ah)
- 14.12 Performance Monitor Register (0Bh)
- 14.13 Digital Loopback Reset Register (0Ch)
- 14.14 LOS/AIS Mode Enable Register (0Dh)
- 14.15 Automatic TAOS Register (0Eh)
- 14.16 Global Control Register (0Fh)
- 14.17 Line Length Channel ID Register (10h)
- 14.18 Line Length Data Register (11h)
- 14.19 Output Disable Register (12h)
- 14.20 AIS Status Register (13h)
- 14.21 AIS Interrupt Enable Register (14h)
- 14.22 AIS Interrupt Status Register (15h)
- 14.23 AWG Broadcast Register (16h)
- 14.24 AWG Phase Address Register (17h)
- 14.25 AWG Phase Data Register (18h)
- 14.26 AWG Enable Register (19h)
- 14.27 Reserved Register (1Ah)
- 14.28 Reserved Register (1Bh)
- 14.29 Reserved Register (1Ch)
- 14.30 Reserved Register (1Dh)
- 14.31 Bits Clock Enable Register (1Eh)
- 14.32 Reserved Register (1Fh)
- 14.33 Status Registers
- 15. Arbitrary Waveform Generator
- 16. JTAG Support
- 17. Boundary Scan Register (BSR)
- 18. Applications
- 19. Characteristics and specifications
- 19.1 Absolute Maximum Ratings
- 19.2 Recommended Operating Conditions
- 19.3 Digital Characteristics
- 19.4 Transmitter Analog Characteristics
- 19.5 Receiver Analog Characteristics
- 19.6 Jitter Attenuator Characteristics
- 19.7 Master Clock Switching Characteristics
- 19.8 Transmit Switching Characteristics
- 19.9 Receive Switching Characteristics
- 19.10 Switching Characteristics - Serial Port
- 19.11 Switching Characteristics - Parallel Port (Multiplexed Mode)
- 19.12 Switching Characteristics- Parallel Port (Non-Multiplexed Mode)
- 19.13 Switching Characteristics - JTAG
- 20. Compliant Recommendations and specifications
- 21. 160-Ball FBGA package dimensions
- 22. 144-Pin LQFP Package dimensions
CS61880
DS450PP3 9
3. PIN DESCRIPTIONS
3.1 Power Supplies
SYMBOL LQFP FBGA TYPE DESCRIPTION
VCCIO
17
92
G1
G14
Power Supply, Digital Interface: Power supply for digital
interface pins; typically 3.3 V
GNDIO 18
91
G4
G11
Ground, Digital Interface:
Power supply ground for the digital interface; typically 0 V
RV0+
RV1+
19
90
H1
H14
Power Supply, Core Circuitry: Power supply for all sub-cir-
cuits except the transmit driver; typically +3.3 V
RGND0
RGND1
20
89
H4
H11
Ground, Core Circuitry:
Ground for sub-circuits except the TX driver; typically 0 V
TV+0 44 N4, P4 Power Supply, Transmit Driver 0
Power supply for transmit driver 0; typically +3.3 V
TGND0 47 N6, P6 Ground, Transmit Driver 0
Power supply ground for transmit driver 0; typically 0 V
TV+1 53 L4, M4 Power Supply, Transmit Driver 1
TGND1 50 L6, M6 Ground, Transmit Driver 1
TV+2 56 L11
M11
Power Supply, Transmit Driver 2
TGND2 59 L9, M9 Ground, Transmit Driver 2
TV+3 65 N11
P11
Power Supply, Transmit Driver 3
TGND3 62 N9, P9 Ground, Transmit Driver 3
TV+4 116 A11
B11
Power Supply, Transmit Driver 4
TGND4 119 A9, B9 Ground, Transmit Driver 4
TV+5 125 C11
D11
Power Supply, Transmit Driver 5
TGND5 122 C9,
D9
Ground, Transmit Driver 5
TV+6 128 C4,
D4
Power Supply, Transmit Driver 6
TGND6 131 C6,
D6
Ground, Transmit Driver 6
TV+7 137 A4, B4 Power Supply, Transmit Driver 7
TGND7 134 A6, B6 Ground, Transmit Driver 7