User Manual
Table Of Contents
- Features
- Description
- 1. Pin Out - 144-Pin LQFP Package
- 2. Pin Out - 160-Ball FBGA Package
- 3. Pin Descriptions
- 4. operation
- 5. Power-up
- 6. Master Clock
- 7. G.772 Monitoring
- 8. Building Integrated Timing Systems (BITS) Clock Mode
- 9. Transmitter
- 10. Receiver
- 11. Jitter Attenuator
- 12. Operational Summary
- 13. Host Mode
- 14. Register Descriptions
- 14.1 Revision/IDcode Register (00h)
- 14.2 Analog Loopback Register (01h)
- 14.3 Remote Loopback Register (02h)
- 14.4 TAOS Enable Register (03h)
- 14.5 LOS Status Register (04h)
- 14.6 DFM Status Register (05h)
- 14.7 LOS Interrupt Enable Register (06h)
- 14.8 DFM Interrupt Enable Register (07h)
- 14.9 LOS Interrupt Status Register (08h)
- 14.10 DFM Interrupt Status Register (09h)
- 14.11 Software Reset Register (0Ah)
- 14.12 Performance Monitor Register (0Bh)
- 14.13 Digital Loopback Reset Register (0Ch)
- 14.14 LOS/AIS Mode Enable Register (0Dh)
- 14.15 Automatic TAOS Register (0Eh)
- 14.16 Global Control Register (0Fh)
- 14.17 Line Length Channel ID Register (10h)
- 14.18 Line Length Data Register (11h)
- 14.19 Output Disable Register (12h)
- 14.20 AIS Status Register (13h)
- 14.21 AIS Interrupt Enable Register (14h)
- 14.22 AIS Interrupt Status Register (15h)
- 14.23 AWG Broadcast Register (16h)
- 14.24 AWG Phase Address Register (17h)
- 14.25 AWG Phase Data Register (18h)
- 14.26 AWG Enable Register (19h)
- 14.27 Reserved Register (1Ah)
- 14.28 Reserved Register (1Bh)
- 14.29 Reserved Register (1Ch)
- 14.30 Reserved Register (1Dh)
- 14.31 Bits Clock Enable Register (1Eh)
- 14.32 Reserved Register (1Fh)
- 14.33 Status Registers
- 15. Arbitrary Waveform Generator
- 16. JTAG Support
- 17. Boundary Scan Register (BSR)
- 18. Applications
- 19. Characteristics and specifications
- 19.1 Absolute Maximum Ratings
- 19.2 Recommended Operating Conditions
- 19.3 Digital Characteristics
- 19.4 Transmitter Analog Characteristics
- 19.5 Receiver Analog Characteristics
- 19.6 Jitter Attenuator Characteristics
- 19.7 Master Clock Switching Characteristics
- 19.8 Transmit Switching Characteristics
- 19.9 Receive Switching Characteristics
- 19.10 Switching Characteristics - Serial Port
- 19.11 Switching Characteristics - Parallel Port (Multiplexed Mode)
- 19.12 Switching Characteristics- Parallel Port (Non-Multiplexed Mode)
- 19.13 Switching Characteristics - JTAG
- 20. Compliant Recommendations and specifications
- 21. 160-Ball FBGA package dimensions
- 22. 144-Pin LQFP Package dimensions
CS61880
48 DS450PP3
28 LOOP1/D1 I LPI1
29 LOOP1/D1 O LPO1
30 LOOP2/D2 I LPT2
31 LOOP2/D2 I LPI2
32 LOOP2/D2 O LPO2
33 LOOP3/D3 I LPT3
34 LOOP3/D3 I LPI3
35 LOOP3/D3 O LPO3
36 LOOP4/D4 I LPT4
37 LOOP4/D4 I LPI4
38 LOOP4/D4 O LPO4
39 LOOP5/D5 I LPT5
40 LOOP5/D5 I LPI5
41 LOOP5/D5 O LPO5
42 LOOP6/D6 I LPT6
43 LOOP6/D6 I LPI6
44 LOOP6/D6 O LPO6
45 LOOP7/D7 I LPT7
46 LOOP7/D7 I LPI7
47 LOOP7/D7 O LPO7
48 - Note 1 LPOEN
49 TCLK1 I TCLK1
50 TPOS1 I TPOS1
51 TNEG1 I TNEG1
52 RCLK1 O RCLK1
53 RPOS1 O RPOS1
54 RNEG1 O RNEG1
55 - Note 2 HIZ1_B
56 LOS1 O LOS1
57 TCLK0 I TCLK0
58 TPOS0 I TPOS0
59 TNEG0 I TNEG0
60 RCLK0 O RCLK0
61 RPOS0 O RPOS0
62 RNEG0 O RNEG0
63 - Note 2 HIZ0_B
64 LOS0 O LOS0
65 MUX I MUX
66 LOS3 O LOS3
67 RNEG3 O RNEG3
68 RPOS3 O RPOS3
69 RCLK3 O RCLK3
70 - Note 2 HIZ3_B
71 TNEG3 I TNEG3
72 TPOS3 I TPOS3
Table 14. Boundary Scan Register (Continued)
BSR
Bit
Pin
Name
Cell
Type
Bit
Symbol