User Manual

CS61880
32 DS450PP3
13. HOST MODE
Host mode allows the CS61880 to be configured
and monitored using an internal register set. (Refer
to Table 1, “Operation Mode Selection,” on
page 10). The term, “Host mode” applies to both
Parallel Host and Serial Host modes.
All of the internal registers are available in both Se-
rial and Parallel Host mode; the only difference is
in the functions of the interface pins, which are de-
scribed in Table 9 on page 32.
Serial port operation is compatible with the serial
ports of most microcontrollers. Parallel port opera-
tion can be configured to be compatible with 8-bit
microcontrollers from Motorola or Intel, with both
multiplexed or non-multiplexed address/data bus-
ses. (Refer to Table 10 on page 34 for host mode
registers).
13.1 SOFTWARE RESET
A software reset can be forced by writing the Soft-
ware Reset Register (0Ah) (See Section 14.11 on
page 36). A software reset initializes all registers to
their default settings and initializes all internal state
machines.
13.2 Serial Port Operation
Serial port host mode operation is selected when
the MODE pin is left open or set to VCC/2. In this
mode, the CS61880 register set is accessed by set-
ting the chip select (CS) pin low and communicat-
ing over the SDI, SDO, and SCLK pins. Timing
over the serial port is independent of the transmit
and receive system timing. Figure 12 illustrates the
format of serial port data transfers.
A read or write is initiated by writing an ad-
dress/command byte (ACB) to SDI. Only the
ADR0-ADR4 bits are valid; bits ADR5-ADR6 are
do not cares. During a read cycle, the register data
addressed by the ACB is output on SDO on the next
eight SCLK clock cycles. During a write cycle, the
data byte immediately follows the ACB.
Data is written to and read from the serial port in
LSB first format. When writing to the port, SDI
data is sampled by the device on the rising edge of
SCLK. The valid clock edge of the data on SDO is
controlled by the CLKE pin. When CLKE is low,
data on SDO is valid on the falling edge of SCLK.
When CLKE is high, data on SDO is valid on the
raising edge of SCLK. The SDO pin is High-Z
when not transmitting. If the host processor has a
Table 9. Host Control Signal Descriptions
HOST CONTROL SIGNAL DESCRIPTIONS
PIN NAME PIN # HARDWARE SERIAL PARALLEL
MODE 11 LOW VDD/2 HIGH
MUX 43 BITSEN0 - MUX
CODEN
/MOT/INTL88CODEN -MOT/INTL
ADDR [4] 12 GND - ADDR[4]
ADDR[3:0] 13-16 ADDR[3:0] - ADDR [3:0]
LOOP[7:0], DATA[7:0] 28-21 LOOP[7:0] - DATA[7:0]
INT
82 Pulled Up INT INT
SDO/ACK/RDY 83 NC SDO ACK/RDY
SDI/DS
/WR 84 GND SDI DS/WR
R/W/RD 85 GND - R/W/RD
SCLK/AS/ALE 86 GND SCLK AS/ALE
JASEL/CS
87 JASEL CS CS