CS61584A CS61584A Dual Dual T1/E1 T1/E1 Line Line Interface Interface Features – AT&T Publication 62411 – ETSI ETS 300 011, 300 233, CTR 12, TBR 13 l Dual T1/E1 Line Interface Volt and 5 Volt Versions l Crystal-less Jitter Attenuator Meets European CTR 12 and ETSI ETS 300 011 Specifications l Matched Impedance Transmit Drivers l Transmitter Tri-state Capability l Common Transmit and ReceiveTransformers for all Modes l Serial and Parallel Host Mode Operation l User-customizable Pulse Shapes l Supports JT
DS261PP5 CS61584A TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 5 RECOMMENDED OPERATING CONDITIONS ....................................................................... 5 ANALOG CHARACTERISTICS ................................................................................................
DS261PP5 10. 11. 12. 13. CS61584A 9.1.2 Mask Registers ................................................................................................... 25 9.1.3 Control A Registers ............................................................................................. 26 9.1.4 Control B Registers ............................................................................................. 27 9.1.5 Arbitrary Waveform Registers .....................................................................
DS261PP5 CS61584A Table 13. CS61584A External Components..................................................................................... 48 Table 14. Quartz Crystal Specifications ........................................................................................... 50 Table 15. Suggested Quartz Crystals............................................................................................... 50 Table 16. Suggested Crystal Oscillators ........................................................
DS261PP5 CS61584A 1. CHARACTERISTICS AND SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Unit - 6.0 V Vin RGND - 0.3 (RV+) + 0.3 V DC Supply (TV+1, TV+2, RV+1, RV+2, AV+, DV+) (Note 1) Input Voltage (Any Pin) Iin -10 10 mA Ambient Operating Temperature Input Current (Any Pin) (Note 2) TA -40 85 °C Storage Temperature Tstg -65 150 °C Notes: 1. Referenced to RGND1, RGND2, TGND1, TGND2, AGND, DGND at 0 V. 2.
DS261PP5 CS61584A ANALOG CHARACTERISTICS (TA = -40 to 85 °C; power supply pins within ±5% of nominal.) Parameter Receiver RTIP/RRING Differential Input Impedance Sensitivity Below DSX-1 (0 dB = 2.
DS261PP5 CS61584A ANALOG CHARACTERISTICS (Continued) Parameter Transmitter (Continued) AMI Output Pulse Amplitudes (Note 16) E1, 75 Ω (Note 17) E1, 120 Ω (Note 18) T1, DSX-1 (Note 19) Recommended Transmitter Output Load (3.3 V) (Note 16) T1 E1, 75 Ω E1, 120 Ω Recommended Transmitter Output Load (5.
DS261PP5 CS61584A DIGITAL CHARACTERISTICS (TA = -40 to 85 °C; power supply pins within ±5% of nominal.) Parameter Symbol Min Max Unit High-Level Input Voltage (Note 23) VIH (DV+) - 0.5 - V Low-Level Input Voltage (Note 23) VIL - 0.5 V High-Level Output Voltage (Iout = -40 µA) (Note 24) VOH (DV+) - 0.3 - V Low-Level Output Voltage (Iout = 1.6 mA) (Note 24) VOL - 0.3 V - ±10 µA Input Leakage Current (Digital pins except J-TMS and J-TDI) Notes: 23.
DS261PP5 t CS61584A t r 90% f 90% Any Digital Output 10% 10% Figure 1. Signal Rise And Fall Characteristics tpw1 RCLK (for CLKE = high) t pwl1 t pwh1 t su1 RPOS RNEG RDATA BPV t h1 RCLK (for CLKE = low) Figure 2. Recovered Clock and Data Switching Characteristics t pw2 t pwh2 TCLK TPOS TNEG TDATA t su2 t h2 Figure 3.
DS261PP5 CS61584A SWITCHING CHARACTERISTICS - SERIAL PORT (TA = -40 to 85 °C; DV+, TV+, RV+ = nominal ± 0.
DS261PP5 CS61584A SWITCHING CHARACTERISTICS - PARALLEL PORT (TA = -40 to 85 °C; TV+, RV+ = nominal ± 0.
DS261PP5 CS61584A PW ash AS PWeh t asd t ased DS t cyc t rws t rwh R/W t ddr t asl t dhr AD0-AD7 (READ) t ahl t ch t cs CS t dsw t asl AD0-AD7 (WRITE) t ahl t dhw t dkd t dkh DTACK (READ and WRITE) Figure 6. Parallel Port Timing - Motorola Mode t cyc ALE t asd PW ash WR t ased t asd PWel RD t cs t ch CS t asl t dhr t ddr AD0-AD7 t ahl Figure 7.
DS261PP5 PW ash CS61584A PW ash AS PWeh t aamir t asd t ased DS t cyc t rws t rwh R/W t asl t ddr t asl t dhr AD0-AD7 (READ) t ahl t ahl t csr t ch CS t dsw t asl t asl AD0-AD7 (WRITE) t ahl t dhw t ahl t dkd t dkh DTACK (READ and WRITE) Figure 9. Parallel Port Timing - Motorola Mode to RAM t cyc ALE t asd PWash PWash WR t aamir t ased t asd PWel RD t csr t ch CS t asl t ddr t asl t dhr AD0-AD7 t ahl t ahl Figure 10.
DS261PP5 CS61584A SWITCHING CHARACTERISTICS - JTAG (TA = -40 to 85 °C; TV+, RV+ = nominal ± 0.3 V; Inputs: Logic 0 = 0 V, Logic 1 = RV+) Parameter Symbol Min Max Unit Cycle Time tcyc 200 - ns J-TMS/J-TDI to J-TCK Rising Setup Time tsu 50 - ns J-TCK Rising to J-TMS/J-TDI Hold Time th 50 - ns J-TCK Falling to J-TDO Valid tdv - 60 ns t cyc J-TCK t su th J-TMS J-TDI t dv J-TDO Figure 12.
DS261PP5 2. OVERVIEW CS61584A The line driver generates waveforms compatible with E1 (CCITT G.703), T1 short haul (DSX-1) and T1 FCC Part 68 Option A (DS1). A single transformer turns ratio is used for all waveform types. The driver internally matches the impedance of the load, providing excellent return loss to insure superior T1/E1 pulse quality.
DS261PP5 The line receiver contains all the necessary clock and data recovery circuits. The jitter attenuator meets AT&T 62411 requirements when using either a 1X or 8X reference clock supplied by either a quartz crystal, crystal oscillator, or external reference at the REFCLK input pin. 2.
DS261PP5 Percent of nominal peak voltage CS61584A 269 ns 120 110 NORMALIZED AMPLITUDE 100 244 ns 194 ns 90 1.0 ANSI T1.102 SPECIFICATION G.703 Specification 80 0.5 50 0 10 CS61584A OUTPUT PULSE SHAPE Nominal Pulse 0 -10 -0.5 -20 0 250 500 750 219 ns 488 ns 1000 TIME (nanoseconds) Figure 14.
DS261PP5 The transmitter impedance changes with the line length options in order to match the load impedance (75 Ω for E1 coax, 100 Ω for T1, 120 Ω for E1 shielded twisted pair), providing a minimum of 14 dB return loss for T1 and E1 frequencies during the transmission of both marks and spaces. This improves signal quality by minimizing reflections from the transmitter.
DS261PP5 the CLKE pin determines the clock polarity where the output data is stable and valid as shown in Table 2. During Host mode operation, the polarity is established by the CLKE bit in the Control A register. When CLKE is low, RPOS and RNEG (or RDATA) are valid on the rising edge of RCLK.
DS261PP5 6. REFERENCE CLOCK The CS61584A requires a reference clock with a minimum accuracy of ±100 ppm for T1 and E1 applications. This clock can be either a 1X clock (i.e., 1.544 MHz or 2.048 MHz), or can be a 8X clock (i.e., 12.352 MHz or 16.384 MHz) as selected by the 1XCLK pin. This clock may be supplied from internal system timing or a CMOS crystal oscillator and input to the REFCLK pin. An 8X quartz crystal may be connected across the REFCLK and XTALOUT pins and the 1XCLK pin set low.
DS261PP5 8.3 Bipolar Violation Detection During Host mode operation, a bipolar violation (BPV) is detected by the receiver and reported using the Latched-BPV bit in the Status registers. If CODER = 1 in the Control A registers, the RNEG pin becomes the BPV output strobe pin that is set high for one bit period on detection of a BPV.
DS261PP5 response to a Loss of Signal condition for either channel is activated by setting bit 1 of the channel 1 Mask register to 1. 8.8 Local Loopback Selecting LLOOP causes the TCLK, TPOS, and TNEG (or TDATA) inputs to be looped back through the jitter attenuator (if enabled) to the RCLK, RPOS, and RNEG (or RDATA) outputs. The receive line interface is ignored, but data at TPOS and TNEG (or TDATA) continues to be transmitted to the line interface at TTIP and TRING.
DS261PP5 CS61584A state. LOS will go high, and the status register will be reset, but the Control, Mask, and Arbitrary Waveform registers remain unchanged. The channel not in power down and the processor port will still to operate normally. lished by the SAD[7:4] pins. The four least significant bits of the address specify the register address in the range of 0x00 to 0x09 for the selected device. Parallel port option is compatible with Motorola and Intel 8-bit, multiplexed address/data bus.
DS261PP5 Latched-LOS: Set high on the rising edge of the loss of signal condition. Reading the Status register clears the Latched-LOS bit and deactivates the INT pin. Refer to the timing diagram in Figure 18. AIS: Set high while the alarm indication signal is detected. Reading the Status register does not clear Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0 CS61584A the AIS bit. An AIS interrupt is generated only on the falling edge of the AIS alarm condition.
DS261PP5 Latched-AIS: Set high on the rising edge of the alarm indication signal condition. Reading the Status register clears the Latched-AIS bit and deactivates the INT pin. Refer to the timing diagram in Figure 18. Latched-BPV: Indicates a bipolar violation has been received since the last read of the Status register. Reading the Status register clears the Latched-BPV bit and deactivates the INT pin. This bit is set only when the line code decoder is enabled in the Control A register.
DS261PP5 CS61584A AAO: The Automatic All-Ones (AAO) bit in the Mask Register (Channel 1, bit 1) causes an unframed all-ones pattern to be output at the RPOS and RNEG (or RDATA) pins when the receiver is in a loss of signal (LOS) condition. CODER: Controls the coder mode function. The TPOS, TNEG, RPOS, and RNEG pins are active when the transparent mode is enabled. The TDATA, RDATA, AIS, and BPV pins are active when the coder mode is enabled. 9.1.
DS261PP5 CS61584A Factory Test: Must be cleared for normal device operation. LLOOP2 simultaneously causes all ones to be output from RPOS/RNEG (RDATA). 9.1.4 LLOOP2: Controls the local loopback #2 function for the channel. Includes the line driver, line receiver, and jitter attenuator, if enabled. See LLOOP1, above, for receive all ones function. Control B Registers The Control B registers are read-write registers and are shown in Table 8.
DS261PP5 sate for waveform degradation that may result from non-standard cables, transformers, or protection circuitry. Arbitrary waveform generation is enabled when the CON[3:0] line configuration selection in the Control B register is set to one of four arbitrary waveform modes (See the Transmitter section). The arbitrary pulse shape of mark (a transmitted "1") is specified by describing the pulse shape across three Unit Intervals (UIs). One UI in DS1 applications is 648 ns (1.
DS261PP5 tude information written for phases 13 and 14 of each UI is ignored. Examples of arbitrary waveforms are illustrated in Figure 19. The amplitude of each phase segment is described by a 7-bit, 2’s complement number (bit 8 is ignored). A positive value describes pulse amplitude and a negative value describes pulse undershoot. For DSX-1 applications with CON[3:0] = 1010, the typical output voltage step is 73 mV/LSB across the secondary (line side) of the transformer.
DS261PP5 9.2 Serial Port Operation Serial port operation in Host mode is selected when the MODE pin is set high and the P/S pin is set low. In this mode, the CS61584A register set is accessed by setting the chip select (CS) pin low and communicating over the SDI, SDO, and SCLK pins. Timing over the serial port is independent of the transmit and receive system timing. Figure 21 illustrates the format of serial port data transfers.
DS261PP5 9.3 Parallel Port Operation Parallel port operation in Host mode is selected when the MODE and P/S pins are set high. In this mode, the CS61584A register set is accessed using an 8-bit, multiplexed bi-directional address/data bus AD[7:0]. Timing over the serial port is independent of the transmit and receive system timing. The device is compatible with both Intel and Motorola bus formats.
DS261PP5 10.1 JTAG Data Registers (DR) The test data registers are the Boundary-Scan Register (BSR), the Device Identification Register (DIR), and the Bypass Register (BR). Boundary Scan Register: The BSR is connected in parallel to all the digital I/O pins, and provides the mechanism for applying/reading test patterns to/from the board traces. The BSR is 62 bits long and is initialized and read using the instruction SAMPLE/PRELOAD.
DS261PP5 MSB LSB 31 28 27 12 11 10 00000110011011100001000011001001 4 bits 16 bits 11 bits BIT #(s) 31-28 27-14 13-12 11-1 0 Function Version Number Part Number Derivative Code Manufacturer Number Constant Logic ‘1’ Total Bits 4 14 2 11 1 Table 11. Device Identification Register Bypass Register: The Bypass register consists of a single bit, and provides a serial path between J-TDI and J-TDO, bypassing the BSR. This allows bypassing specific devices during certain board-level tests.
DS261PP5 10.5 Run-Test/Idle State When the TAP controller is in this state and a rising edge is applied to J-TCK, the controller enters the Exit1-DR state if J-TMS is high or the Shift-DR state if J-TMS is low. This is a controller state between scan operations. Once in this state, the controller remains in the state as long as J-TMS is held low. The instruction register and all test data registers retain their previous state.
DS261PP5 10.10 Pause-DR State The pause state allows the test controller to temporarily halt the shifting of data through the test data register in the serial path between J-TDI and JTDO. For example, this state could be used to allow the tester to reload its pin memory from disk during application of a long test sequence. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
DS261PP5 10.16 Exit1-IR State This is a temporary state. While in this state, if JTMS is held high, a rising edge applied to J-TCK causes the controller to enter the Update-IR state, which terminates the scanning process. If J-TMS is held low and a rising edge is applied to J-TCK, the controller enters the Pause-IR state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. 10.
DS261PP5 CS61584A TCK Run-Test/Idle Exit1-IR Update-IR Shift-IR Exit2-IR Pause-IR Exit1-IR Shift-IR Capture-IR Select-IR-Scan Run-Test/Idle Select-DR-Scan Controller state Test-Logic-Reset TMS TDI Parallel Input to IR IR shift-register IDCODE Parallel output of IR New Instruction Parallel Input to TDR Parallel output of TDR Old data TDR shift-register Instruction register Register selected TDO enable Inactive Act Inactive Active Inactive TDO = Don’t care or undefined Figure 25.
DS261PP5 CS61584A TCK Test-Logic-Reset Select-IR-Scan Select-DR-Scan Run-Test/Idle Exit1-DR Update-DR Shift-DR Exit2-DR Pause-DR Exit1-DR Shift-DR Capture-DR Select-DR-Scan Controller state Run-Test/Idle TMS TDI Parallel Input to IR IR shift-register Instruction Parallel output of IR IDCODE Parallel Input to TDR TDR shift-register Parallel output of TDR Old data Test data register Register Selected TDO enable New data Inactive Active Inactive Active Inactive TDO = Don’t care o
DS261PP5 CS61584A 11.
DS261PP5 Hardware Mode Host Mode Serial Port CS61584A Host Mode Parallel Port Host Mode Serial Port Hardware Mode Host Mode Parallel Port DGND1 DGND1 DGND1 CON01 not used AD3 DV+ DV+ DV+ TAOS2 TAOS1 SPOL SDI AD2 AD1 DGND3 CON02 DGND3 not used DGND3 AD4 LLOOP SDO AD0 CON11 not used AD5 RLOOP2 RLOOP1 SCLK INT RD(DS) INT CON12 CON21 not used not used AD6 AD7 ALE(AS) ATTEN1 CS CS CON22 not used not used not used not used CON31 not used WR(R/W) RCLK1 RCLK1 RCLK1 n
DS261PP5 CS61584A T1/E1 Data Inputs and Outputs RCLK1, RCLK2 - Receive Clock (PLCC pins 10, 59; TQFP pins 1, 48) RPOS1, RPOS2 - Receive Positive Data (PLCC pins 11, 58; TQFP pins 2, 47) RNEG1, RNEG2 - Receive Negative Data (PLCC pins 12, 57; TQFP pins 3, 46) The receiver recovered clock and NRZ digital data from RTIP and RRING is output on these pins. During Hardware mode operation, the CLKE pin determines the clock edge on which RPOS and RNEG are stable and valid.
DS261PP5 CS61584A REFCLK - External Reference Clock Input (PLCC pin 36; TQFP pin 26) Input reference clock for the receive and jitter attenuator circuits. When 1XCLK is high, REFCLK must be a 1X clock (i.e., 1.544 MHz ±100 ppm for T1 applications or 2.048 MHz ±100 ppm for E1 applications). When 1XCLK is set low, REFCLK must be an 8X clock (i.e., 12.352 MHz ±100 ppm for T1 applications or 16.384 MHz ±100 ppm for E1 applications). The REFCLK input also determines the transmission rate when TAOS is asserted.
DS261PP5 CS61584A PD1, PD2 - Power Down [Hardware mode] (PLCC pins 24, 45; TQFP pins 15, 34) Setting PD high places the channel in a low power, inactive state. Power down forces the transmitter, receiver, and jitter attenuator to the reset state. All device outputs are forced to a high impedance state to facilitate circuit board testing.
DS261PP5 CS61584A INT - Receive Alarm Interrupt [Host mode] (PLCC pin 7; TQFP pin 63) An interrupt is generated to flag the host processor when a Status register changes state. The interrupt is cleared by reading the Status register. The logic level for an active interrupt alarm is controlled by the IPOL pin. The INT pin is an open drain output and must be tied to the appropriate supply through a resistor.
DS261PP5 CS61584A Status AIS1, AIS2 - Alarm Indication Signal [Host mode] (PLCC pins 15, 54; TQFP pins 6, 43) The AIS indication goes high when the receiver detects 99.9% ones density in a 5.3 ms period (< 9 zeros in 8192 bits). The AIS indication returns low when the receiver detects ≥ 9 zeros in 8192 bits. BPV1, BPV2 - Bipolar Violation [Host mode] (PLCC pins 12, 57; TQFP pins 3, 46) The BPV indication goes high for one RCLK bit period when a bipolar violation is detected in the received signal.
DS261PP5 CS61584A 12. PACKAGE DIMENSIONS 64L LQFP PACKAGE DRAWING E E1 D D1 1 e B ∝ A A1 L DIM A A1 B D D1 E E1 e* L MIN --0.002 0.007 0.461 0.390 0.461 0.390 0.016 0.018 0.000° ∝ * Nominal pin pitch is 0.50 mm INCHES NOM 0.55 0.004 0.008 0.472 BSC 0.393 BSC 0.472 BSC 0.393 BSC 0.020 BSC 0.024 4° MAX 0.063 0.006 0.011 0.484 0.398 0.484 0.398 0.024 0.030 7.000° MIN --0.05 0.17 11.70 9.90 11.70 9.90 0.40 0.45 0.00° MILLIMETERS NOM 1.40 0.10 0.20 12.0 BSC 10.0 BSC 12.0 BSC 10.0 BSC 0.50 BSC 0.
DS261PP5 CS61584A 68L PLCC PACKAGE DRAWING e D2/E2 E1 E B A1 D1 D DIM A A1 B D D1 D2 E E1 E2 e MIN 0.165 0.090 0.013 0.985 0.950 0.890 0.985 0.950 0.890 0.040 INCHES NOM 0.1825 0.105 0.017 0.990 0.953 0.910 0.990 0.953 0.910 0.050 A MAX 0.200 0.130 0.021 0.995 0.958 0.930 0.995 0.958 0.930 0.060 MIN 4.191 2.286 0.3302 25.019 24.13 22.606 25.019 24.13 22.606 1.016 MILLIMETERS NOM 4.6355 2.667 0.4318 25.146 24.206 23.114 25.146 24.206 23.114 1.270 MAX 5.08 3.302 0.533 25.273 24.333 23.622 25.
DS261PP5 CS61584A 13. APPLICATIONS 2 2 MODE RESET PD[1:2] CLKE REFCLK 1XCLK 2 2 3 2 3 ATTEN[0:1] RLOOP[1:2] LLOOP TAOS[1:2] CON[0:2]1 CON[0:2]2 LOS[1:2] Hardware Control Clock Generator T1 1:N TTIP1 TCLK1 TPOS1 TNEG1 RCLK1 RPOS1 RNEG1 Framer 0.47µ F TRING1 Channel 1 RTIP1 R1 transmit T2 1:N 0.47µ F receive RRING1 TTIP2 TCLK2 TPOS2 TNEG2 RCLK2 RPOS2 RNEG2 Framer C1 R2 0.47µ F TRING2 RTIP2 Channel 2 T3 1:N C2 R3 transmit T4 1:N 0.47µ F receive RRING2 AV+ AGND 0.
DS261PP5 CS61584A Vcc 2 REFCLK 1XCLK 2 MODE RESET ZTX[1:2] LOS[1:2] P/S IPOL SPOL CS INT SCLK SDO SDI Host Control Clock Generator TTIP1 TCLK1 TPOS1 (TDATA1) TNEG1 (AIS1) RCLK1 RPOS1 (RDATA1) RNEG1 (BPV1) Framer TRING1 Channel 1 RTIP1 C1 R1 transmit T2 1:N 0.47µ F receive RRING1 TTIP2 TCLK2 TPOS2 (TDATA2) TNEG2 (AIS2) RCLK2 RPOS2 (RDATA2) RNEG2 (BPV2) Framer T1 1:N 0.47µ F TRING2 RTIP2 Channel 2 R2 0.47µ F T3 1:N C2 R3 transmit T4 1:N 0.
DS261PP5 13.2 Power Supply As shown in Figure 27, the CS61584A operates from a 3.3 Volt or 5.0 Volt supply. Separate power and ground pins provide internal isolation. The best way to configure the power supplies is to connect all of the supply pins together at the device. The various ground pins must not be more negative than AGND. A 4.99 kΩ ±1% resistor must be connected from BGREF to ground to provide an internal current reference.
DS261PP5 13.5 Transformers 13.7 Recommended transformer specifications are shown in Table 17. Based on these specifications, the transformers recommended for use with the CS61584A are listed in Table 18. Turns ratio (-IL3 and IQ3) Turns ratio (-IL5 and IQ5) Primary inductance Primary leakage inductance Secondary leakage inductance Interwinding capacitance ET-constant 1:2 step-up transmit 1:2 step-down receive 1:1.15 step-up transmit 1:1.15 step-down receive 1.5 mH min at 772 kHz 0.
DS261PP5 Turns Ratio 1:2 (-IL3 and -IQ3) Manufacturer Halo Pulse Engineering Schott Valor 1:1.15 (-IL5 and -IQ5) Halo Pulse Engineering Schott Valor Part Number TD08-1205A TG26-1205N1 PE-65351 PE-65771 PE-65835 PE-65761 PE-65821 PE-65861 T1016 T1073 67129300 67115090 ST5095 ST5175T TD38-1505A PE-65388 PE-65770 PE-65838 PE-68674 PE-65870 T1016 T1072 67124840 ST5112 ST5171T CS61584A Package Type 1.5 kV through-hole, single 2 kV surface mount, dual 1.5 kV through-hole, single 1.
CS61584A ORDERING INFORMATION Model Operating Voltage CS61584A-IL3 3.3 V CS61584A-IL5 5.0 V Package Temperature 68-pin PLCC CS61584A-IQ3 -40 to +85 °C 3.3 V CS61584A-IQ3Z (Lead Free) 64-pin LQFP CS61584A-IQ5 5.
CS61584A REVISION HISTORY Revision Date Changes PP5 JAN 2001 Preliminary Release F1 SEP 2005 Updated device ordering info. Updated legal notice. Added MSL data.. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable.
