CS61583 Dual T1/E1 Line Interface Features General Description • • The CS61583 is a dual line interface for T1/E1 applications, designed for high-volume cards where low power and high density are required. Each channel features individual control and status pins which eliminates the need for external microprocessor support. The matched impedance drivers reduce power consumption and provide substantial return loss to insure superior T1/E1 pulse quality.
CS61583 Table of Contents Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Specifications Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . 3 Digital Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Analog Specifications Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Jitter Attenuator . . . . . . . . . . .
CS61583 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Units - 6.0 V Vin RGND - 0.3 (RV+) + 0.3 V Iin -10 10 mA Ambient Operating Temperature TA -40 85 °C Storage Temperature Tstg -65 150 °C DC Supply (TV+1, TV+2, RV+1, RV+2, AV+, DV+) (Note 1) Input Voltage (Any Pin) Input Current (Any Pin) (Note 2) WARNING: Operations at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1.
CS61583 DIGITAL CHARACTERISTICS (TA = -40 to 85 °C; power supply pins within ±5% of nominal) Parameter Symbol Min Typ Max Units High-Level Input Voltage (Note 7) VIH (DV+)-0.5 - - V Low-Level Input Voltage (Note 7) VIL - - 0.5 V VOH (DV+)-0.3 - - V VOL - - 0.3 V - - ±10 µA High-Level Output Voltage (Digital pins) IOUT = -40 µA (Note 8) Low-Level Output Voltage (Digital pins) IOUT = 1.
CS61583 ANALOG SPECIFICATIONS (TA = -40 to 85 °C; power supply pins within ±5% of nominal) Parameter Min Typ Max Units 2.14 2.7 2.4 2.37 3.0 3.0 2.6 3.3 3.6 V V V - 76.6 57.4 90.6 - Ω Ω Ω - 0.005 0.008 0.010 0.015 - UI UI UI UI (Notes 14 and 21) (DSX-1 only) 12.6 15 17.9 dBm (Notes 14 and 21)) (DSX-1 only) -29 -38 - dB -5 -5 0.2 - 0.
CS61583 SWITCHING CHARACTERISTICS - T1 CLOCK/DATA (TA = -40 to 85 °C; power supply pins within ±5% of nominal; Inputs: Logic 0 = 0V, Logic 1 = DV+) (See Figures 1, 2, and 3) Parameter Symbol Min Typ Max Units ftclk - 1.
CS61583 tr Any Digital Output tf 90% 90% 10% 10% Figure 1. Signal Rise and Fall Characteristics t pw1 RCLK (CLKE = 1) RPOS RNEG RDATA BPV t pwl1 t pwh1 t su1 t h1 RCLK (CLKE =0) Figure 2. Recovered Clock and Data Switching Characteristics t pw2 t pwh2 TCLK t su2 t h2 TPOS TNEG TDATA Figure 3.
CS61583 SWITCHING CHARACTERISTICS - JTAG (TA = - 40 ° to 85 ° C; TV+, RV+ = nominal ±0.3V; Inputs: Logic 0 = 0V, Logic 1 = RV+) (See Figure 4) Parameter Symbol Min Typ Max Units Cycle Time tcyc 200 - - ns J-TMS/J-TDI to J-TCK rising setup time tsu 50 - - ns J-TCK rising to J-TMS/J-TDI hold time th 50 - - ns J-TCK falling to J-TDO valid tdv - - 50 ns t cyc J-TCK t su J-TMS th J-TDI t dv J-TDO Figure 4.
CS61583 OVERVIEW support. The following pin control options are available on a per channel basis: line length selection, coder mode, jitter attenuator location, transmit all ones, local loopback, and remote loopback. The CS61583 is a dual line interface for T1/E1 applications, designed for high-volume cards where low power and high density are required.
CS61583 tional benefit of the internal impedance matching is a 50 percent reduction in power consumption compared to implementing return loss using external resistors that causes the transmitter to drive the equivalent of two line loads. The line receiver contains all the necessary clock and data recovery circuits. The jitter attenuator meets AT&T 62411 requirements when using a 1X or 8X reference clock supplied by either a crystal oscillator or external reference at the REFCLK input pin.
CS61583 Percent nominal peak voltage NORMALIZED AMPLITUDE 1.0 of 269 ns 120 110 ANSI T1.102 SPECIFICATION 0.5 100 244 ns 194 ns 90 G.703 Specification 80 0 50 CS61583 OUTPUT PULSE SHAPE -0.5 0 500 250 750 1000 10 TIME (nanoseconds) Nominal Pulse 0 Figure 6. Typical Pulse Shape at DSX-1 Cross Connect during the transmission of both marks and spaces. This improves signal quality by minimizing reflections from the transmitter.
CS61583 ter will output a maximum of 50 mA-rms, as required by European specification BS6450. RECEIVER The receiver extracts data and clock from the T1/E1 signal on the line interface and outputs clock and synchronized data to the system. The signal is detected differentially across the receive transformer and can be recovered over the entire range of short haul cable lengths. The transmit and receive transfomer specifications are identical and are presented in the Applications section.
CS61583 age incoming frequency (e.g. following a device reset) the attenuator will tolerate a minimum of 22 UIs before the overflow/underflow mechanism occurs. For T1/E1 line cards used in high-speed mutiplexers (e.g., SONET and SDH), the jitter attenuator is typically used in the transmit path. The attenuator can accept a transmit clock with gaps ≤ 28 UIs and a transmit clock burst rate of ≤ 8 MHz.
CS61583 Alarm Indication Signal In coder mode, the TNEG pin becomes the alarm indication signal (AIS) output controlled by the receiver. The receiver detects the AIS condition on observation of 99.9% ones density in a 5.3 ms period (< 9 zeros in 8192 bits) and sets the AIS pin high. The AIS condition is exited when ≥ 9 zeros are detected in 8192 bits. Bipolar Violation Detection In coder mode, the RNEG pin becomes the bipolar violation (BPV) strobe output controlled by the receiver.
CS61583 receive circuitry is calibrated if REFCLK and TCLK are present. shift operation. Note that if J-TDI is floating, an internal pull-up resistor forces the pin high. JTAG BOUNDARY SCAN JTAG Data Registers (DR) The test data registers are the Boundary-Scan Register (BSR), the Device Identification Register (DIR), and the Bypass Register (BR). Board testing is supported through JTAG boundary scan.
CS61583 The first bit (shifted in first) selects between an output-enabled state (bit set to 1) or high-impedance state (bit set to 0). The second bit shifted in contains the test data that may be output on the pin. Therefore, two J-TCK cycles are required to load test data for each output pin.
CS61583 JTAG Instructions and Instruction Register (IR) The instruction register (2 bits) allows the instruction to be shifted into the JTAG circuit. The instruction selects the test to be performed or the data register to be accessed or both. The valid instructions are shifted in LSB first and are listed below: IR CODE 00 01 10 11 INSTRUCTION EXTEST SAMPLE/PRELOAD IDCODE BYPASS EXTEST Instruction: The EXTEST instruction allows testing of off-chip circuitry and boardlevel interconnect.
CS61583 instruction register and all test data registers retain their previous state. When J-TMS is high and a rising edge is applied to J-TCK, the controller moves to the Select-DR state. When the TAP controller is in this state and a rising edge is applied to J-TCK, the controller enters the Exit1-DR state if J-TMS is high or the Shift-DR state if J-TMS is low. Select-DR-Scan State This is a temporary controller state.
CS61583 The test data register selected by the current instruction retains its previous value during this state. The instruction does not change in this state. parallel output of this register from the shift-register path on the falling edge of J-TCK. The data held at the latched parallel output changes only in this state. Pause-DR State The pause state allows the test controller to temporarily halt the shifting of data through the test data register in the serial path between J-TDI and J-TDO.
CS61583 The test data register selected by the current instruction retains its previous value during this state. The instruction does not change in this state. When the controller is in this state and a rising edge is applied to J-TCK, the controller enters the Exit1-IR state if J-TMS is held high, or remains in the Shift-IR state if J-TMS is held low. Exit1-IR State This is a temporary state.
CS61583 TCK Run-Test/Idle Exit1-IR Update-IR Shift-IR Exit2-IR Pouse-IR Exit1-IR Shift-IR Capture-IR Select-IR-Scan Run-Test/Idle Select-DR-Scan Controller state Test-Logic-Reset TMS TDI Parallel Input to IR IR shift-register Parallel output of IR IDCODE New Instruction Parallel Input to TDR Parallel output of TDR TDR shift-register Old data Register selected TDO enable Instruction register Inactive Act Inactive Active Inactive TDO = Don't care or undefined Figure 13.
CS61583 TCK Test-Logic-Reset Select-IR-Scan Select-DR-Scan Run-Test/Idle Exit1-DR Update-DR Shift-DR Exit2-DR Pouse-DR Exit1-DR Shift-DR Capture-DR Select-DR-Scan Controller state Run-Test/Idle TMS TDI Parallel Input to IR IR shift-register Parallel output of IR Instruction IDCODE Parallel Input to TDR TDR shift-register Parallel output of TDR Old data Register Selected TDO enable New data Test data register Inactive Active Inactive Active Inactive TDO = Don't care or undefined
CS61583 PIN DESCRIPTIONS DGND1 CON01 DV+ TAOS2 DGND3 TAOS1 CON02 LLOOP2 CON11 LLOOP1 CON12 RLOOP1 CON21 ATTEN1 CON22 not used AMI1 RCLK1 not used RPOS1/RDATA1 RCLK2 9 RNEG1/BPV1 TCLK1 7 5 3 1 67 65 63 61 RPOS2/RDATA2 RNEG2/BPV2 11 59 13 57 LOS1 15 55 TNEG2/AIS2 J-TDO 17 53 LOS2 TPOS1/TDATA1 TNEG1/AIS1 DGND2 J-TDI 19 CS61583 68-Pin PLCC Top View AMI2 J-TCK J-TMS 23 47 TTIP2 25 45 21 TV+1 TGND1 TRING1 TPOS2/TDATA2 49 TTIP1 CODER1 51 TCLK2 27 29 31 33 3
CS61583 DGND1 CON01 TAOS2 TAOS1 LLOOP2 LLOOP1 RLOOP1 ATTEN1 RCLK1 RPOS1/RDATA1 RNEG1/BPV1 TCLK1 TPOS1/TDATA1 TNEG1/AIS1 LOS1 J-TDO DGND2 J-TDI TTIP1 TV+1 TGND1 TRING1 CODER1 ATTEN0 RTIP1 RRING1 RV+1 RGND1 AGND1 BGREF AGND2 AV+ 24 64 1 2 62 60 58 56 54 52 50 48 46 4 44 6 CS61583 42 8 64-Pin TQFP 40 10 38 Top View 12 36 14 34 16 18 20 22 24 26 28 30 32 DV+ DGND3 CON02 CON11 CON12 CON21 CON22 AMI1 RCLK2 RPOS2/RDATA2 RNEG2/BPV2 TCLK2 TPOS2/TDATA2 TNEG2/AIS2 LOS2 AMI2 J-TCK J-TMS TT
CS61583 Power Supplies AGND1, AGND2 : Analog Ground (PLCC pins 31, 33; TQFP pins 21, 23) Analog supply ground pins. AV+ : Analog Power Supply (PLCC pin 34; TQFP pin 24) Analog supply pin for the internal bandgap reference and timing generation circuits. BGREF : Bandgap Reference (PLCC pin 32; TQFP pin 22) This pin is used by the internal bandgap reference and must be connected to ground by a 4.99kΩ ±1% resistor to provide an internal current reference.
CS61583 TCLK1, TCLK2 : Transmit Clock (PLCC pins 13, 56; TQFP pins 4, 45) TPOS1, TPOS2 : Transmit Positive Data (PLCC pins 14, 55; TQFP pins 5, 44) TNEG1, TNEG2 : Transmit Negative Data (PLCC pins 15, 54; TQFP pins 6, 43) The transmit clock and data are input to these pins. The signal is driven to the line interface at TTIP and TRING. Data at TPOS and TNEG are sampled on the falling edge of TCLK.
CS61583 CODER1, CODER2 : Coder Mode Configuration (PLCC pins 24, 45; TQFP pins 15, 34) Setting CODER high causes the Coder Mode to be enabled. In Coder Mode, the transmit and receive data appears in NRZ format on TDATA and RDATA, respectively. These pins also enable the corresponding AMI pin.
CS61583 LOS1, LOS2 : Loss of Signal (PLCC pins 16, 53; TQFP pins 7, 42) The LOS indication goes high when 175 ± 15 consecutive zeros are received on the line interface. The LOS indication returns low when a minimum 12.5% ones density signal over 175 ± 75 bit periods with no more than 100 consecutive zeros is received. Test J-TCK : JTAG Test Clock (PLCC pin 51; TQFP pin 40) Data on pins J-TDI and J-TDO is valid on the rising edge of J-TCK. When J-TCK is stopped low, all JTAG registers remain unchanged.
CS61583 PHYSICAL DIMENSIONS DIM A 68 pin PLCC MILLIMETERS INCHES MIN MAX MIN MAX 4.20 5.08 .165 .200 A1 2.29 3.30 .090 .130 B 0.38 0.53 .015 .021 D 24.79 25.30 .976 .996 D1 24.13 24.38 .950 .960 E 24.79 25.30 .976 .996 E1 24.13 24.38 .950 .960 e 1.27 u 23.37 23.62 .920 .930 x 1.067 1.219 .042 .048 68 pin PLCC E1 E .050 y .51 .020 z .51 x 45° x 3 .
CS61583 D D1 64-Pin TQFP MILLIMETERS E E1 64 A1 C B e MIN - MAX 0.068 0.00 - 0.00 - B 0.14 0.26 0.006 0.010 C 0.077 11.70 0.177 12.30 0.003 0.461 0.007 0.484 D1 E 10.00 10.00 0.394 0.394 11.70 12.30 0.461 0.484 E1 e 10.00 0.40 10.00 0.60 0.394 0.016 0.394 0.024 L 0.35 0.70 0.014 0.028 ∝ 0° 12° 0° 12° A Terminal Detail 1 L 30 MAX 1.
CS61583 APPLICATIONS CLKE REFCLK 1XCLK RESET ATTEN2 AMI1 CON11 ATTEN1 CODER1 CON01 TAOS1 CON21 RLOOP1 LLOOP1 AMI2 CODER2 CON12 CON02 TAOS2 CON22 RLOOP2 LLOOP2 Hardware Control Clock Generator TTIP1 0.47µF TCLK1 TPOS1 (TDATA1) TNEG1 (AIS1) RCLK1 RPOS1 (RDATA1) RNEG1 (BPV1) Framer TRING1 Channel 1 RTIP1 transmit T2 1:1.15 0.47µF receive RRING1 TTIP2 TCLK2 TPOS2 (TDATA2) TNEG2 (AIS2) RCLK2 RPOS2 (RDATA2) RNEG2 (BPV2) Framer R1 T1 1:1.15 C1 R2 0.
CS61583 resistor must be connected from BGREF to ground to provide an internal current reference. De-coupling and filtering of the power supplies is crucial for the proper operation of the analog circuits. A capacitor should be connected between each supply and its respective ground. For capacitors smaller than 1 µF, use mylar or ceramic capacitors and place them as close as possible to their respective power supply pins.
CS61583 Turns Ratio Manufacturer Part Number PE-65388 PE-65770 PE-65838 1:1.15 Pulse Engineering PE-68674 Schott PE-65870 67124840 Valor ST5112 Package Type 1.5 kV through-hole, single 1.5 kV through-hole, single extended temperature 3.0 kV through-hole, single extended temperature 1.5 kV surface-mount, dual extended temperature 1.5 kV surface-mount, dual 1.5 kV through-hole, single extended temperature 2.
CDB61583 Dual Line Interface Evaluation Board Features General Description • Socketed CS61583 Dual Line Interface • All Required Components for CS61583 The evaluation board includes a socketed CS61583 dual line interface device and all support components necessary for evaluation. The board is powered by an external +5 Volt supply. Evaluation The board may be configured for 100Ω twisted-pair T1, 75Ω coax E1, or 120Ω twisted-pair E1 operation.
CDB61583 POWER SUPPLY As shown on the evaluation board schematic in Figures 1-5, power is supplied to the board from an external +5 Volt supply connected to the two binding posts labeled V+ and GND. Zener diode Z1 protects the components on the board from reversed supply connections and over-voltage damage. Capacitor C16 provides power supply decoupling and ferrite bead L1 isolates the CS61583 and buffer supplies.
CDB61583 reset can be used to initialize the control logic. Both channels are powered up after exiting reset. TRANSMIT CIRCUIT The transmit clock and data signals are supplied on BNC inputs labeled TCLK(1,2), TPOS(1,2), and TNEG(1,2). When the coder mode is disabled, data is supplied on the TPOS(1,2) and TNEG(1,2) BNC inputs in RZ format.
CDB61583 Crystal Oscillator A crystal oscillator may be inserted at socket U4 in the orientation indicated by the silkscreen. Header J14 must be jumpered in the "OSC" position to provide connectivity to the REFCLK pin of the CS61583. The SW2 switch position labeled "1XCLK" must be open (logic 0) for 8-X clock operation or closed (logic 1) for 1-X clock operation. transformers installed at locations T1-T4. They are socketed to permit the evaluation of other transformers.
CDB61583 4. Closing a DIP switch on SW2, SW3, and SW4 towards the label sets the CS61583 control pin of the same name to logic 1. 5. When performing a manual loopback of the recovered signal to the transmit signal at the BNC connectors, the recovered data must be valid on the falling edge of RCLK to properly latch the data in the transmit direction. To accomplish this, the SW2 switch position labeled "CLKE" must be closed (logic 1). 6.
CDB61583 R29 R C LK 1 3 5 1 .1 R30 RPOS1 (R D A T A 1 ) 17 U2 C 26 1 0 0 pF J2 15 .1 µF U2 5 1 .1 4 16 U2 C 29 10 0 p F J5 6 TPOS (T D A T A 1) 8 A IS 1 D1 LED 470 1 2 5 1.1 3 4 J-T D O VD+ R 26 47 K J-T D I C3 .1 µF VA+ 2 Q2 R7 R5 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 5 1 .1 5 1 .1 J7 1 3 D2 LED R38 R39 12 C31 1 00 p F VA+ 3 2 Q1 U2 R6 LOS1 U7 CS61583 CHANNEL 1 14 U2 C30 100pF J6 TNEG 13 C28 1 00 p F J4 T C LK 1 GND U2 5 1 .
CDB61583 J16 VA+ 11 L2 U3 VCC 1 20 E N A 19 U 3 10 GND R C LK 2 C 32 1 00pF 13 51.1 J1 7 R 42 7 U3 ENA R 41 9 C 33 100pF 5 1.1 5 U3 C 34 100pF R 43 C 15 RPOS2 (R D A T A 2) J18 .1µF 15 RNEG2 (B P V 2) 51 .1 J19 14 U7 C S 61583 C HANN EL 2 100pF N /C -3 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 16 4 18 2 U3 C 36 1 00pF R 50 R 51 51 .1 51 .1 4 3 10K A M I2 J-T C K J-T M S R 28 5 1.1 J13 VD+ R 27 47K C 13 VA+ 1 1 T4 VD+ 1 3 D7 .
CDB61583 VD+ J2 4 VD+ R56 5 1 .1 26 24 22 20 18 16 14 12 10 8 6 4 2 CS SD1 SCLK R 55 3 .9 2 k J26 SD 0 25 IN T 2 3 21 19 17 15 13 11 9 7 5 3 1 100 pF R 40 5 1 .
CDB61583 29 R V +1 30 RGND1 31 AGND1 32 R 10 BGREF 4.99k 3 3 AGND2 34 AV+ 35 RESET 36 R E F C LK 37 R LO O P 2 1X C L K 38 1X C LK 39 RGND2 40 R V +2 U7 CS61583 TIMING CIRCUITRY C5 .1 µF C8 VD+ Y1 .1µF C6 .1µF C7 1 .0µF VD+ J 10 (m ust be jum pe red) VD+ 1 SW 6 RLOO P2 R 11 SW 1 10 K 2 R23 47 K VD+ VD+ VA+ U4 C 14 .1µF 2 4 1 3 J14 VCC REFCLK 8 GND J15 N otes: A crystal o scillator at U 4 o r e xtern al refere nce sup plied a t J15 m ust be p rovided .
CDB61583 GND V+ J23 J22 VA+ C 16 4 7µF Z1 VD+ L1 VD+ P rototyping A rea Figure 5.
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