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Preliminary Product Information

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

http://www.cirrus.com

3/25/08

10:56

CS5571

±2.5 V / 5 V, 100 kSps, 16-bit, High-throughput

∆Σ

ADC

Features & Description

 Single-ended Analog Input

 On-chip Buffers for High Input Impedance

 Conversion Time = 10 µS

 Settles in One Conversion

 Linearity Error = 0.0008%

 Signal-to-Noise = 92 dB

 S/(N + D) = 91 dB

 DNL = ±0.1 LSB Max.

 Simple three/four-wire serial interface

 Power Supply Configurations:

- Analog: +5V/GND; IO: +1.8V to +3.3V

- Analog: ±2.5V; IO: +1.8V to +3.3V

 Power Consumption:

- ADC Input Buffers On: 85 mW

- ADC Input Buffers Off: 60 mW

General Description

The CS5571 is a single-channel, 16-bit analog-to-digital

converter capable of 100 kSps conversion rate. The input

accepts a single-ended analog input signal. On-chip buff-

ers provide high input impedance for both the AIN input

and the VREF+ input. This significantly reduces the drive

requirements of signal sources and reduces errors due to

source impedances. The CS5571 is a delta-sigma convert-

er capable of switching multiple input channels at a high

rate with no loss in throughput. The ADC uses a low-laten-

cy digital filter architecture. The filter is designed for fast

settling and settles to full accuracy in one conversion. The

converter's 16-bit data output is in serial format, with the

serial port acting as either a master or a slave. The convert-

er is designed to support bipolar, ground-referenced

signals when operated from ±2.5V analog supplies.

The converter can operate from an analog supply of 0-5V

or from ±2.5V. The digital interface supports standard logic

operating from 1.8, 2.5, or 3.3 V.

ORDERING INFORMATION:

See Ordering Information on page 34.

AIN

ACOM

SCLK

SMODE

VREF+

VREF-

RDY

OSC/CLOCK

GENERATOR

CONV

BP/UP

DIGITAL CONTROL

SERIAL

INTERFACE

ADC

DIGITAL

FILTER

LOGIC

MCLK

SDO

RST

DITHER

DCR

VLR

V1-

V2-

BUFEN

V2+

V1+

CS5571

TST

VLR2

MAR ‘08

DS768PP1

Summary of content (34 pages)

PAGE 1
3/25/08 10:56 CS5571 ±2.5 V / 5 V, 100 kSps, 16-bit, High-throughput ∆Σ ADC Features & Description General Description Single-ended Analog Input The CS5571 is a single-channel, 16-bit analog-to-digital converter capable of 100 kSps conversion rate. The input accepts a single-ended analog input signal. On-chip buffers provide high input impedance for both the AIN input and the VREF+ input. This significantly reduces the drive requirements of signal sources and reduces errors due to source impedances.
PAGE 2
3/25/08 10:56 CS5571 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ANALOG CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SWITCHING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DIGITAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
/25/08 10:56 CS5571 LIST OF FIGURES Figure 1. SSC Mode - Read Timing, CS remaining low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. SSC Mode - Read Timing, CS falling after RDY falls . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. SEC Mode - Continuous SCLK Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. SEC Mode - Discontinuous SCLK Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
3/25/08 10:56 CS5571 1. CHARACTERISTICS AND SPECIFICATIONS • Min / Max characteristics and specifications are guaranteed over the specified operating conditions. • Typical characteristics and specifications are measured at nominal supply voltages and TA = 25°C. • VLR = 0 V. All voltages measured with respect to 0 V. ANALOG CHARACTERISTICS TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 16 MHz; SMODE = VL.
PAGE 5
3/25/08 10:56 CS5571 ANALOG CHARACTERISTICS (CONTINUED) TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 16 MHz; SMODE = VL. DITHER = VL unless otherwise stated; BUFEN = V1+ unless otherwise stated. Connected per Figure 6.
PAGE 6
3/25/08 10:56 CS5571 SWITCHING CHARACTERISTICS TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF. Parameter Master Clock Frequency Internal Oscillator External Clock Symbol Min Typ Max Unit XIN fclk 12 0.5 14 16 16 16.
PAGE 7
3/25/08 10:56 CS5571 SWITCHING CHARACTERISTICS (CONTINUED) TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.
PAGE 8
3/25/08 10:56 CS5571 SWITCHING CHARACTERISTICS (CONTINUED) TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.
PAGE 9
3/25/08 10:56 CS5571 SWITCHING CHARACTERISTICS (CONTINUED) TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.
PAGE 10
3/25/08 10:56 CS5571 MCLK t21 RDY t15 t20 CS SCLK(i) t17 SDO t18 t19 MSB LSB Figure 4. SEC Mode - Discontinuous SCLK Read Timing (Not to Scale) DIGITAL CHARACTERISTICS TA = TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.
PAGE 11
3/25/08 10:56 CS5571 GUARANTEED LOGIC LEVELS TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF. Guaranteed Limits Parameter Sym VL Min 3.3 1.9 2.5 1.6 1.8 1.2 Typ Max Unit Conditions Logic Inputs Minimum High-level Input Voltage: Maximum Low-level Input Voltage: VIH VIL V 3.3 1.1 2.5 0.95 1.8 0.
PAGE 12
3/25/08 10:56 CS5571 RECOMMENDED OPERATING CONDITIONS (VLR = 0V, see Note 17) Parameter Symbol Min Typ Max Unit (Note 17) V1+ V2+ V1V2- V1+ V2V1+ V2- 4.75 4.75 - 5.0 5.0 0 0 5.25 5.25 - V V V V (Note 17) V1+ V2+ V1V2- V1+ V2V1+ V2- +2.375 +2.375 -2.375 -2.375 +2.5 +2.5 -2.5 -2.5 +2.625 +2.625 -2.625 -2.625 V V V V VREF 2.4 4.096 4.2 V Single Analog Supply DC Power Supplies: Dual Analog Supplies DC Power Supplies: Analog Reference Voltage 17. 18.
PAGE 13
3/25/08 10:56 CS5571 2. OVERVIEW The CS5571 is a 16-bit analog-to-digital converter capable of 100 kSps conversion rate. The analog input accepts a single-ended input with a magnitude of ±VREF / 2 volts. The device is capable of switching multiple input channels at a high rate with no loss in throughput. The ADC uses a low-latency digital filter architecture. The filter is designed for fast settling and settles to full accuracy in one conversion. The converter is a serial output device.
PAGE 14
3/25/08 10:56 CS5571 Once a conversion is completed and RDY falls, RDY will return high when all the bits of the data word are emptied from the serial port or if the conversion data is not read and CS is held low, RDY will go high two MCLK cycles before the end of conversion. RDY will fall at the end of the next conversion when new data is put into the port register. See Serial Port on page 26 for information about reading conversion data. Conversion performance can be affected by several factors.
PAGE 15
3/25/08 10:56 CS5571 3.3 Voltage Reference The voltage reference for the CS5571 can range from 2.4 volt to 4.2 volts. A 4.096 volt reference is required to achieve the specified signal-to-noise performance. Figure 6 and Figure 7 illustrate the connection of the voltage reference with either a single +5 V analog supply or with ±2.5 V.
PAGE 16
3/25/08 10:56 CS5571 3.5 Output Coding Format The reference voltage directly defines the input voltage range in both the unipolar and bipolar configurations. In the unipolar configuration (BP/UP low), the first code transition occurs 0.5 LSB above zero, and the final code transition occurs 1.5 LSBs below VREF. In the bipolar configuration (BP/UP high), the first code transition occurs 0.5 LSB above -VREF and the last transition occurs 1.5 LSBs below +VREF.
PAGE 17
3/25/08 10:56 CS5571 3.6 Typical Connection Diagrams The following figure depicts the CS5571 powered from bipolar analog supplies, +2.5 V and - 2.5 V. +2.048 V 0V CS5571 -2.048 V 49.9 AIN 150pF 4700pF C0G SMODE 2k CS 5 SCLK 5 ACOM SDO RDY (V+) Buffers On BUFEN +2.5 V CONV (V-) Buffers Off BP/UP DITHER +4.096 Voltage Reference (NOTE 1) VREF+ 10 µF RST 0.1 µF 50 MCLK VREFTST -2.5 V +3.3 V to +1.8 V +2.5 V V1+ VL 10 0.1 µF V2+ 0.1 µF 0.1 µF 10 V20.
PAGE 18
3/25/08 10:56 CS5571 The following figure depicts the CS5571 part powered from a single 5V analog supply and configured for unipolar measurement. 0 V to +2.048 V CS5571 49.9 AIN 150pF SMODE 4700pF C0G CS 2k 4 SCLK CS3003 / CS3004 4 ACOM SDO RDY (V+) Buffers On BUFEN +5 V CONV (V-) Buffers Off BP/UP DITHER +4.096 Voltage Reference (NOTE 1) VREF+ 10 µF RST 0.1 µF 50 MCLK VREFTST +3.3 V to 1.8 V +5 V V1+ 0.1 µF VL 10 V2+ 0.1 µF 0.1 µF V20.1 µF X7R DCR V1- VLR2 VLR NOTES 1.
PAGE 19
3/25/08 10:56 CS5571 The following figure depicts the CS5571 part powered from a single 5V analog supply and configured for bipolar measurement, referenced to a common mode voltage of 2.5 V. +4.548 V +2.5 V +0.452 V CS5571 49.9 AIN 150pF 4700pF C0G 2k SMODE CS3003 / CS3004 Common Mode Voltage (2.5 V Typ.) CS 4 SCLK 49.9 ACOM 150pF 4700pF C0G 4 2k SDO RDY CS3003 / CS3004 (V+) Buffers On CONV BUFEN +5 V CAL BP/UP (V-) Buffers Off DITHER +4.
PAGE 20
3/25/08 10:56 CS5571 3.7 AIN & VREF Sampling Structures The CS5571 uses on-chip buffers on the AIN and VREF+ inputs. Buffers provide much higher input impedance and therefore reduce the amount of drive current required from an external source. This helps minimize errors. The Buffer Enable (BUFEN) pin determines if the on-chip buffers are used or not. If the BUFEN pin is connected to the V1+ supply, the buffers will be enabled. If the BUFEN pin is connected to the V1- pin, the buffers are off.
PAGE 21
3/25/08 10:56 CS5571 Figures 11, 12, and 13 indicate the spectral performance of the CS5571 with a 0 dB, -6 dB and - 12 dB 5.55 kHz input signal. In each case, the captured data was windowed with a seven-term window function that exhibits 4.3 dB of attenuation before being processed by the FFT. 0 0 5.55 kHz, 0 dB 32k Samples @ 100 kSps -20 5.
PAGE 22
3/25/08 10:56 CS5571 Figures 14 and 15 illustrate the small signal performance of the CS5571 with a 5.55 kHz signal at -80 dB down. Figure 14 is with DITHER on and Figure 15 is with DITHER off. At -80 dB the signal is 1/10,000 of full scale, having a peak-to-peak magnitude of only a few codes.
PAGE 23
3/25/08 10:56 CS5571 Figure 18 illustrates a test signal of 5.55 kHz, 116.3 dB down, which is only 6.3 microvolts peak to peak, or about 1/10 of a code width. The converter can reliably digitize this signal because of its excellent DNL and proper dither. 0 -20 -40 -60 -80 -100 -120 -140 -160 0 10k 20k 30k Frequency (Hz) 40k 50k Figure 18. Spectral Performance, -116.3 dB Dither On Figure 19 is a spectral plot of the converter with its input grounded.
PAGE 24
3/25/08 10:56 CS5571 Figure 20 illustrates a noise histogram of 4096 samples with the input signal adjusted to almost the exact center of a code with DITHER on. Figure 21 illustrates a noise histogram of 4096 samples with the input signal at the center of a code with DITHER off. Notice that with a signal at the center of a code that the converter outputs the same code over 96% of the time.
PAGE 25
3/25/08 10:56 CS5571 3.10 Digital Filter Characteristics The digital filter is designed for fast settling, therefore it exhibits very little in-band attenuation. The filter attenuation is 1.040 dB at 50 kHz when sampling at 100 kSps. 0.00 -0.0414 dB fs = 100 kSps -0.1660 dB -0.25 -0.3740 dB -0.50 -0.6660 dB -0.75 -1.00 -1.040 dB -1.25 -1.50 0 10k 20k 30k 40k 50k Frequency (Hz) Figure 24. CS5571 Digital Filter Response (DC to fs/2) 0.00 -0.001650 dB fs = 100 kSps -0.00700 dB -0.01 -0.
PAGE 26
3/25/08 10:56 CS5571 3.11 Serial Port The serial port on the CS5571 can operate in two different modes: synchronous self clock (SSC) mode & synchronous external clock (SEC) mode. The serial port must be placed into the SEC mode if the offset and gain registers of the converter are to be read or written. The converter must be idle when reading or writing to the on-chip registers. 3.11.1 SSC Mode If the SMODE pin is high (SMODE = VL), the serial port operates in the SSC (Synchronous Self Clock) mode.
PAGE 27
3/25/08 10:56 CS5571 3.13 Using the CS5571 in Multiplexing Applications The CS5571 is a delta-sigma A/D converter. Delta-sigma converters use oversampling as means to achieve high signal-to-noise performance. This means that once a conversion is started, the converter takes many samples to compute the resulting output word. The analog input for the signal to be converted must remain active during the entire conversion until RDY falls.
PAGE 28
3/25/08 10:56 CS5571 At the same time the converter is performing a conversion on a channel from one bank of multiplexers, the second multiplexer bank is used to select the channel for the next conversion. This configuration allows the buffer amplifier for the second multiplexer bank to fully settle while a conversion is being performed on the channel from the first multiplexer bank.
PAGE 29
3/25/08 10:56 CS5571 3.14 Synchronizing Multiple Converters Many measurement systems have multiple converters that need to operate synchronously. The converters should all be driven from the same master clock. In this configuration, the converters will convert synchronously if the same CONV signal is used to drive all the converters, and CONV falls on a falling edge of MCLK.
PAGE 30
3/26/08 14:22 CS5571 4.
PAGE 31
3/25/08 10:56 CS5571 BP/UP – Bipolar/Unipolar Select, Pin 11 The BP/UP pin determines the span and the output coding of the converter. When set high to select BP (bipolar), the input span of the converter is -2.048 volts to +2.048 volts (assuming the voltage reference is 4.096 volts) and output data is coded in two's complement format. When set low to select UP (unipolar), the input span is 0 to +2.048 and the output data is coded in binary format.
PAGE 32
3/25/08 10:56 CS5571 SCLK – Serial Clock Input/Output, Pin 23 The SMODE pin determines whether the SCLK signal is an input or an output signal. SCLK determines the rate at which data is clocked out of the SDO pin. If the converter is in SSC mode, the SCLK frequency will be determined by the master clock frequency of the converter (either MCLK or the internal oscillator). In SEC mode, the user determines the SCLK frequency.
PAGE 33
3/25/08 10:56 CS5571 5. PACKAGE DIMENSIONS 24L SSOP PACKAGE DRAWING N D E11 A2 E e b2 SIDE VIEW A ∝ A1 L END VIEW SEATING PLANE 1 2 3 TOP VIEW DIM A A1 A2 b D E E1 e L MIN -0.002 0.064 0.009 0.311 0.291 0.197 0.022 0.025 0° ∝ INCHES NOM -0.006 0.068 -0.323 0.307 0.209 0.026 0.03 4° MAX 0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.030 0.041 8° MIN -0.05 1.62 0.22 7.90 7.40 5.00 0.55 0.63 0° MILLIMETERS NOM -0.13 1.73 -8.20 7.80 5.30 0.65 0.75 4° NOTE MAX 2.13 0.25 1.88 0.38 8.50 8.
PAGE 34
3/25/08 10:56 CS5571 6. ORDERING INFORMATION Model CS5571-ISZ Linearity Temperature Conversion Time Throughput Package .0008% -40 to +85 °C 10 µs 100 kSps 24-pin SSOP 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Peak Reflow Temp MSL Rating* Max Floor Life 260 °C 3 7 Days CS5571-ISZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 8. REVISION HISTORY Revision PP1 Date MAR 2008 Changes Preliminary release.