Manual

ManualsBrandsCirrus Logic ManualsHardwareCS5560

Table Of Contents

Preliminary Product Information

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

http://www.cirrus.com

5/4/09

CS5560

±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput

ΔΣ

ADC

Features & Description

 Differential Analog Input

 On-chip Buffers for High Input Impedance

 Conversion Time = 20 μS

 Settles in One Conversion

 Linearity Error = 0.0005%

 Signal-to-Noise = 110 dB

 24 Bits, No Missing Codes

 Simple three/four-wire serial interface

 Power Supply Configurations:

- Analog: +5 V / GND; IO: +1.8 V to +3.3 V

- Analog: ±2.5 V; IO: +1.8 V to +3.3 V

 Power Consumption:

- ADC Input Buffers On: 90 mW

- ADC Input Buffers Off: 60 mW

General Description

The CS5560 is a single-channel, 24-bit analog-to-digital

converter capable of 50 kSps conversion rate. The input

accepts a fully differential analog input signal. On-chip

buffers provide high input impedance for both the AIN in-

puts and the VREF+ input. This significantly reduces the

drive requirements of signal sources and reduces errors

due to source impedances. The CS5560 is a delta-sigma

converter capable of switching multiple input channels at

a high rate with no loss in throughput. The ADC uses a

low-latency digital filter architecture. The filter is designed

for fast settling and settles to full accuracy in one conver-

sion. The converter's 24-bit data output is in serial form,

with the serial port acting as either a master or a slave. The

converter is designed to support bipolar, ground-refer-

enced signals when operated from ±2.5V analog supplies.

The converter can operate from an analog supply of 0-5V

or from ±2.5V. The digital interface supports standard log-

ic operating from 1.8, 2.5, or 3.3 V.

ORDERING INFORMATION:

See Ordering Information on page 32.

AIN+

AIN-

SCLK

SMODE

VREF+

VREF-

RDY

OSC/CLOCK

GENERATOR

CONV

BP/UP

DIGITAL CONTROL

SERIAL

INTERFACE

ADC

DIGITAL

FILTER

LOGIC

MCLK

SDO

RST

SLEEP

VLR

VLR2

V1-

V2-

BUFEN

V2+

V1+

CS5560

TST

DCR

MAY ‘09

DS713PP2

Summary of content (32 pages)

PAGE 1
5/4/09 CS5560 ±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ΔΣ ADC Features & Description General Description  Differential Analog Input The CS5560 is a single-channel, 24-bit analog-to-digital converter capable of 50 kSps conversion rate. The input accepts a fully differential analog input signal. On-chip buffers provide high input impedance for both the AIN inputs and the VREF+ input. This significantly reduces the drive requirements of signal sources and reduces errors due to source impedances.
PAGE 2
5/4/09 CS5560 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ANALOG CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SWITCHING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DIGITAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
5/4/09 CS5560 LIST OF FIGURES Figure 1. SSC Mode - Read Timing, CS remaining low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. SSC Mode - Read Timing, CS falling after RDY falls . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. SEC Mode - Continuous SCLK Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. SEC Mode - Discontinuous SCLK Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5.
PAGE 4
5/4/09 CS5560 1. CHARACTERISTICS AND SPECIFICATIONS • Min / Max characteristics and specifications are guaranteed over the specified operating conditions. • Typical characteristics and specifications are measured at nominal supply voltages and TA = 25°C. • VLR = 0 V. All voltages with respect to 0 V. ANALOG CHARACTERISTICS TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 16 MHz; SMODE = VL.
PAGE 5
/4/09 CS5560 ANALOG CHARACTERISTICS (CONTINUED) TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 16 MHz; SMODE = VL.; BUFEN = V1+ unless otherwise stated. Connected per Figure 6.
PAGE 6
5/4/09 CS5560 SWITCHING CHARACTERISTICS TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF. Parameter Symbol Min Typ Max Unit XIN fclk 12 0.5 14 16 16 16.
PAGE 7
5/4/09 CS5560 SWITCHING CHARACTERISTICS (CONTINUED) TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.
PAGE 8
5/4/09 CS5560 SWITCHING CHARACTERISTICS (CONTINUED) TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.
PAGE 9
5/4/09 CS5560 SWITCHING CHARACTERISTICS (CONTINUED) TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.
PAGE 10
5/4/09 CS5560 MCLK t21 RDY t15 t20 CS SCLK(i) t17 SDO t18 t19 MSB LSB Figure 4. SEC Mode - Discontinuous SCLK Read Timing (Not to Scale) DIGITAL CHARACTERISTICS TA = TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V Parameter Symbol Min Typ Max Unit Input Leakage Current Iin - - 2 µA Digital Input Pin Capacitance Cin - 3 - pF Digital Output Pin Capacitance Cout - 3 - pF DIGITAL FILTER CHARACTERISTICS TA = TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.
PAGE 11
5/4/09 CS5560 GUARANTEED LOGIC LEVELS TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF. Guaranteed Limits Parameter Sym VL Min 3.3 1.9 2.5 1.6 1.8 1.2 Typ Max Unit Conditions Logic Inputs Minimum High-level Input Voltage: Maximum Low-level Input Voltage: VIH VIL V 3.3 1.1 2.5 0.95 1.8 0.
PAGE 12
5/4/09 CS5560 RECOMMENDED OPERATING CONDITIONS (VLR = 0V, see Note 15) Parameter Symbol Min Typ Max Unit (Note 15) V1+ V2+ V1V2- V1+ V2V1+ V2- 4.75 4.75 - 5.0 5.0 0 0 5.25 5.25 - V V V V (Note 15) V1+ V2+ V1V2- V1+ V2V1+ V2- +2.375 +2.375 -2.375 -2.375 +2.5 +2.5 -2.5 -2.5 +2.625 +2.625 -2.625 -2.625 V V V V VREF 2.4 4.096 4.2 V Single Analog Supply DC Power Supplies: Dual Analog Supplies DC Power Supplies: Analog Reference Voltage 15. 16.
PAGE 13
5/4/09 CS5560 2. OVERVIEW The CS5560 is a 24-bit analog-to-digital converter capable of 50 kSps conversion rate. The device is capable of switching multiple input channels at a high rate with no loss in throughput. The ADC uses a low-latency digital filter architecture. The filter is designed for fast settling and settles to full accuracy in one conversion. The converter is a serial output device. The serial port can be configured to function as either a master or a slave.
PAGE 14
5/4/09 CS5560 To perform only one conversion, CONV should return high at least 20 master clock cycles before RDY falls. Once a conversion is completed and RDY falls, RDY will return high when all the bits of the data word are emptied from the serial port or if the conversion data is not read and CS is held low, RDY will go high two MCLK cycles before the end of conversion. RDY will fall at the end of the next conversion when new data is put into the port register.
PAGE 15
5/4/09 CS5560 3.2 Clock The CS5560 can be operated from its internal oscillator or from an external master clock. The state of MCLK determines which clock source will be used. If MCLK is tied low, the internal oscillator will start and be used as the clock source for the converter. If an external CMOS-compatible clock is input into MCLK the converter will power down the internal oscillator and use the external clock. If the MCLK pin is held high, the internal oscillator will be held in the stopped state.
PAGE 16
5/4/09 CS5560 3.4 Analog Input The analog input of the converter is fully differential with a peak-to-peak input of 4.096 volts on each input. Therefore, the differential, peak-to-peak input is 8.192 volts. This is illustrated in Figure 6 and Figure 7. These diagrams also illustrate a differential buffer amplifier configuration for driving the CS5560.
PAGE 17
5/4/09 CS5560 3.6 Typical Connection Diagrams The following figure depicts the CS5560 powered from bipolar analog supplies, +2.5 V and - 2.5 V. 4700pF C0G R1 C1 AIN+ 47pF 4.99k 4.99k R1 C1 CS5560 49.9 49.9 +2.048 V 0V -2.048 V SMODE +2.048 V 0V -2.048 V CS 5 SCLK AIN47pF 4700pF C0G 4.99k 5 SDO RDY 4.99k (V+) Buffers On CONV BUFEN +2.5 V BP/UP (V-) Buffers Off +4.096 Voltage Reference (NOTE 1) SLEEP VREF+ 10 µF RST 0.1 µF 50 MCLK VREFTST -2.5 V +3.3 V to +1.8 V +2.
PAGE 18
5/4/09 CS5560 The following figure depicts the CS5560 device powered from a single 5V analog supply. 4700pF C0G 49.9 2.048 V AIN+ 47pF CS5560 4.548 V 2.5 V +0.452 V 4.99k SMODE +4.548 V 2.5 V +0.452 V 49.9 CS 4 SCLK AIN4.096 V 47pF 4700pF C0G 4.99k 4 SDO RDY (V+) Buffers On CONV BUFEN +5 V BP/UP (V-) Buffers Off SLEEP +4.096 Voltage Reference (NOTE 1) VREF+ 10 µF RST 0.1 µF 50 MCLK VREFTST +3.3 V to 1.8 V +5 V V1+ 0.1 µF VL 10 V2+ 0.1 µF 0.1 µF V20.
PAGE 19
5/4/09 CS5560 3.7 AIN & VREF Sampling Structures The CS5560 uses on-chip buffers on the AIN+, AIN-, and the VREF+ inputs. Buffers provide much higher input impedance and therefore reduce the amount of drive current required from an external source. This helps minimize errors. The Buffer Enable (BUFEN) pin determines if the on-chip buffers are used or not. If the BUFEN pin is connected to the V1+ supply, the buffers will be enabled. If the BUFEN pin is connected to the V1- pin, the buffers are off.
PAGE 20
5/4/09 CS5560 Figure 9 through Figure 16 illustrate the performance of the converter with various input signal magnitudes. 5.55 kHz, -0 dB 32k Samples @ 50 kSps Frequency (Hz) Frequency (Hz) Figure 9. Spectral Performance, 0 dB Figure 10. Spectral Performance, -6 dB 5.55 kHz, -12 dB 32k Samples @ 50 kSps 5.55 kHz, -20 dB 32k Samples @ 50 kSps Frequency (Hz) Figure 11. Spectral Performance, -12 dB 5.55 kHz, -40 dB 32k Samples @ 50 kSps Frequency (Hz) Figure 13.
PAGE 21
5/4/09 CS5560 Figure 15 illustrates the device with a small signal 1/1,000,000 of full scale. The signal input for Figure 15 is about 8.2 microvolts peak to peak, or about 17 codes peak to peak. Figure 16 illustrates the converter with a signal at about 2.6 microvolts peak to peak, or about 5 codes peak to peak. The CS5560 achieves superb performance with this small signal. And the noise floor exhibits no spurious components due to digital interference from the on chip logic. 5.
PAGE 22
5/4/09 CS5560 Figure 17 illustrates the noise floor of the converter from 0.1 Hz to 25 kHz. While the plot does exhibit some 1/f noise at lower frequencies, the noise floor is entirely free of spurious frequency content due to digital activity inside the chip. Figure 16 illustrates a noise histogram of 32,768 samples. -60 Shorted Input 1M Samples @ 50 kSps 64 Averages -80 -100 -120 -140 -160 -180 0.1 1 10 100 Frequency (Hz) 1k 10k 25k Figure 17.
PAGE 23
5/4/09 CS5560 3.9 Digital Filter Characteristics The digital filter is designed for fast settling, therefore it exhibits very little in-band attenuation. The filter attenuation is 1.040 dB at 25 kHz when sampling at 50 kSps. 0.0 fs = 50 kSps -0.0414 dB Attenuation (dB) -0.2 -0.166 dB -0.4 -0.3725 dB -0.6 -0.664 dB -0.8 -1.0 -1.040 dB -1.2 0 5k 10k 15k 20k 25k Frequency (Hz) Figure 19. CS5560 Digital Filter Response (DC to fs/2) -0.001646 dB fs = 50 kSps -0.00663 dB -0.0149 dB -0.
PAGE 24
5/4/09 CS5560 3.10 Serial Port The serial port on the CS5560 can operate in two different modes: synchronous self clock (SSC) mode & synchronous external clock (SEC) mode. 3.10.1 SSC Mode If the SMODE pin is high (SMODE = VL), the serial port operates in the SSC (Synchronous Self Clock) mode. In the SSC mode the port shifts out conversion data words with SCLK as an output. SCLK is generated inside the converter from MCLK. Data is output from the SDO (Serial Data Output) pin.
PAGE 25
5/4/09 CS5560 3.11 Power Supplies & Grounding The CS5560 can be configured to operate with its analog supply operating from 5V, or with its analog supplies operating from ±2.5V. The digital interface supports digital logic operating from either 1.8V, 2.5V, or 3.3V. Figure 6 on page 17 illustrates the device configured to operate from ±2.5V analog. Figure 7 on page 18 illustrates the device configured to operate from 5V analog.
PAGE 26
5/4/09 CS5560 3.12 Using the CS5560 in Multiplexing Applications The CS5560 is a delta-sigma A/D converter. Delta-sigma converters use oversampling as means to achieve high signal to noise. This means that once a conversion is started, the converter takes many samples to compute the resulting output word. The analog input for the signal to be converted must remain active during the entire conversion until RDY falls.
PAGE 27
5/4/09 CS5560 At the same time the converter is performing a conversion on a channel from one bank of multiplexers, the second multiplexer bank is used to select the channel for the next conversion. This configuration allows the buffer amplifier for the second multiplexer bank to fully settle while a conversion is being performed on the channel from the first multiplexer bank. The multiplexer on the output of the buffer amplifier and the CONV signal can be changed at the same time in this configuration.
PAGE 28
5/4/09 CS5560 4.
PAGE 29
5/4/09 CS5560 BP/UP – Bipolar/Unipolar Select, Pin 11 The BP/UP pin determines the span and the output coding of the converter. When set high to select BP (bipolar), the input span of the converter is -4.096 volts to +4.096 volts fully differential (assuming the voltage reference is 4.096 volts) and output data is coded in two's complement format. When set low to select UP (unipolar), the input span is 0 to +4.096 fully differential and the output data is coded in binary format.
PAGE 30
5/4/09 CS5560 SCLK – Serial Clock Input/Output, Pin 23 The SMODE pin determines whether the SCLK signal is an input or an output signal. SCLK determines the rate at which data is clocked out of the SDO pin. If the converter is in SSC mode, the SCLK frequency will be determined by the master clock frequency of the converter (either MCLK or the internal oscillator). In SEC mode, the user determines the SCLK frequency. If SMODE = VL (SSC Mode), SCLK will be in a high-impedance state when CS is high.
PAGE 31
5/4/09 CS5560 5. PACKAGE DIMENSIONS 24L SSOP PACKAGE DRAWING N D E11 A2 E e b2 SIDE VIEW A ∝ A1 L END VIEW SEATING PLANE 1 2 3 TOP VIEW DIM A A1 A2 b D E E1 e L MIN -0.002 0.064 0.009 0.311 0.291 0.197 0.022 0.025 0° ∝ INCHES NOM -0.006 0.068 -0.323 0.307 0.209 0.026 0.03 4° MAX 0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.030 0.041 8° MIN -0.05 1.62 0.22 7.90 7.40 5.00 0.55 0.63 0° MILLIMETERS NOM -0.13 1.73 -8.20 7.80 5.30 0.65 0.75 4° NOTE MAX 2.13 0.25 1.88 0.38 8.50 8.20 5.60 0.
PAGE 32
5/4/09 CS5560 6. ORDERING INFORMATION Model CS5560-ISZ Linearity Temperature Conversion Time Throughput Package 0.0005% -40 to +85 °C 20 μs 50 kSps 24-pin SSOP 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Peak Reflow Temp MSL Rating* Max Floor Life 260 °C 3 7 Days CS5560-ISZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 8. REVISION HISTORY Revision PP1 PP2 Date MAR 2008 MAY 2009 Changes Preliminary Release.