Instruction Manual

3.3V SWITCHING CHARACTERISTICS
(T
A
= T
MIN
to T
MAX
VA+ = 5V
±
10%; VD+ = 3.3V
±
5%; VA- = -5 V
±
10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C
L
= 50 pF.) (Note 2)
Parameter Symbol Min Typ Max Units
SSC Mode (M/SLP = VD+)
Access Time: CS Low to SDATA out (DRDY = low)
DRDY falling to MSB (CS = low)
t
csd1
t
dfd
-
-
-
2/f
clk
2/fclk
3/f
clk
ns
ns
SDATA Delay Time: SCLK falling to next SDATA bit t
dd1
- 265 400 ns
SCLK Delay Time SDATA MSB bit to SCLK rising t
cd1
-1/f
clk
-ns
Serial Clock (Out) Pulse Width High
Pulse Width Low
t
ph1
t
pl1
-
-
1/f
clk
1/f
clk
-
-
ns
ns
Output Float Delay: CS high to output Hi-Z (Note 16)
SCLK rising to SDATA Hi-Z
t
fd1
t
fd2
-
-
-
1/f
clk
2/f
clk
-
ns
ns
SEC Mode (M/SLP = DGND)
Serial Clock (In) f
sclk
0 - 1.25 MHz
Serial Clock (In) Pulse Width High
Pulse Width Low
t
ph2
t
pl2
200
200
-
-
-
-
ns
ns
Access Time: CS Low to data valid (Note 17) t
csd2
- 100 200 ns
Maximum Delay time: (Note 18)
SCLK falling to new SDATA bit t
dd2
- 400 600 ns
Output Float Delay: CS high to output Hi-Z (Note 16)
SCLK falling to SDATA Hi-Z
t
fd3
t
fd4
-
-
70
320
150
500
ns
ns
CS5505/6/7/8
10 DS59F4
CS5505/6/7/8
10 DS59F7